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Searched refs:writel_relaxed (Results 1 – 25 of 100) sorted by relevance

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/arch/arm/mach-hisi/
Dhotplug.c83 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
88 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN); in set_cpu_hi3620()
93 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
96 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); in set_cpu_hi3620()
100 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
107 writel_relaxed(val, ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
112 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
117 writel_relaxed(val, ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
120 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS); in set_cpu_hi3620()
124 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
[all …]
Dplatsmp.c28 writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2)); in hi3xxx_set_cpu_jump()
112 writel_relaxed(0xe51ff004, virt); /* ldr pc, [pc, #-4] */ in hix5hd2_set_scu_boot_addr()
113 writel_relaxed(jump_addr, virt + 4); /* pc jump phy address */ in hix5hd2_set_scu_boot_addr()
148 writel_relaxed(0xe51ff004, virt); in hip01_set_boot_addr()
149 writel_relaxed(jump_addr, virt + 4); in hip01_set_boot_addr()
173 writel_relaxed(remap_reg_value, ctrl_base + REG_SC_CTRL); in hip01_boot_secondary()
Dplatmcpm.c92 writel_relaxed(data, fabric + FAB_SF_MODE); in hip04_set_snoop_filter()
122 writel_relaxed(data, sys_dreq); in hip04_boot_secondary()
132 writel_relaxed(data, sys_dreq); in hip04_boot_secondary()
220 writel_relaxed(data, sysctrl + SC_CPU_RESET_REQ(cluster)); in hip04_cpu_kill()
327 writel_relaxed(hip04_boot_method[0], relocation); in hip04_smp_init()
328 writel_relaxed(0xa5a5a5a5, relocation + 4); /* magic number */ in hip04_smp_init()
329 writel_relaxed(__pa_symbol(secondary_startup), relocation + 8); in hip04_smp_init()
330 writel_relaxed(0, relocation + 12); in hip04_smp_init()
/arch/arm/mach-qcom/
Dplatsmp.c69 writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL); in scss_release_secondary()
70 writel_relaxed(0, base + SCSS_CPU1CORE_RESET); in scss_release_secondary()
71 writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP); in scss_release_secondary()
114 writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL); in kpssv1_release_secondary()
120 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
122 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
127 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
132 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
137 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
142 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
[all …]
/arch/arm/kernel/
Dsmp_twd.c39 writel_relaxed(0, twd_base + TWD_TIMER_CONTROL); in twd_shutdown()
46 writel_relaxed(TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT, in twd_set_oneshot()
57 writel_relaxed(DIV_ROUND_CLOSEST(twd_timer_rate, HZ), in twd_set_periodic()
59 writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL); in twd_set_periodic()
70 writel_relaxed(evt, twd_base + TWD_TIMER_COUNTER); in twd_set_next_event()
71 writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL); in twd_set_next_event()
85 writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT); in twd_timer_ack()
163 writel_relaxed(0x1, twd_base + TWD_TIMER_CONTROL); in twd_calibrate_rate()
166 writel_relaxed(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER); in twd_calibrate_rate()
229 writel_relaxed(0, twd_base + TWD_TIMER_CONTROL); in twd_timer_setup()
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/arch/arm/mach-omap2/
Dsram.c64 writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ in is_sram_locked()
65 writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */ in is_sram_locked()
66 writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */ in is_sram_locked()
69 writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */ in is_sram_locked()
70 writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */ in is_sram_locked()
71 writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */ in is_sram_locked()
72 writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2); in is_sram_locked()
73 writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0); in is_sram_locked()
Domap4-common.c84 writel_relaxed(0, dram_sync); in omap4_mb()
119 writel_relaxed(readl_relaxed(dram_sync), dram_sync); in omap_interconnect_sync()
120 writel_relaxed(readl_relaxed(sram_sync), sram_sync); in omap_interconnect_sync()
177 writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL); in gic_dist_disable()
183 writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL); in gic_dist_enable()
203 writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT); in gic_timer_retrigger()
205 writel_relaxed(1, twd_base + TWD_TIMER_COUNTER); in gic_timer_retrigger()
207 writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL); in gic_timer_retrigger()
Domap-mpuss-lowpower.c122 writel_relaxed(addr, pm_info->wkup_sar_addr); in set_cpu_wakeup_addr()
148 writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr); in scu_pwrst_prepare()
187 writel_relaxed(save_state, pm_info->l2x0_sar_addr); in l2x0_pwrst_prepare()
200 writel_relaxed(l2x0_saved_regs.aux_ctrl, in save_l2x0_context()
202 writel_relaxed(l2x0_saved_regs.prefetch_ctrl, in save_l2x0_context()
424 writel_relaxed((omap_type() != OMAP2_DEVICE_TYPE_GP) ? 1 : 0, in omap4_mpuss_init()
486 writel_relaxed(startup_pa, sar_base + in omap4_mpuss_early_init()
489 writel_relaxed(startup_pa, sar_base + in omap4_mpuss_early_init()
Domap-wakeupgen.c83 writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 + in wakeupgen_writel()
89 writel_relaxed(val, sar_base + offset + (idx * 4)); in sar_writel()
265 writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET); in omap4_irq_save_context()
267 writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET); in omap4_irq_save_context()
271 writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET); in omap4_irq_save_context()
273 writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET); in omap4_irq_save_context()
278 writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET); in omap4_irq_save_context()
298 writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET); in omap5_irq_save_context()
300 writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET); in omap5_irq_save_context()
305 writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); in omap5_irq_save_context()
[all …]
/arch/arm/mach-shmobile/
Dpm-rcar-gen2.c109 writel_relaxed(bar, p + CA15BAR); in rcar_gen2_pm_init()
110 writel_relaxed(bar | SBAR_BAREN, p + CA15BAR); in rcar_gen2_pm_init()
113 writel_relaxed((readl_relaxed(p + CA15RESCNT) & in rcar_gen2_pm_init()
118 writel_relaxed(bar, p + CA7BAR); in rcar_gen2_pm_init()
119 writel_relaxed(bar | SBAR_BAREN, p + CA7BAR); in rcar_gen2_pm_init()
122 writel_relaxed((readl_relaxed(p + CA7RESCNT) & in rcar_gen2_pm_init()
/arch/arm/common/
Dsa1111.c214 writel_relaxed(stat0, mapbase + SA1111_INTSTATCLR0); in sa1111_irq_handler()
218 writel_relaxed(stat1, mapbase + SA1111_INTSTATCLR1); in sa1111_irq_handler()
272 writel_relaxed(ie, mapbase + SA1111_INTEN0); in sa1111_unmask_irq()
291 writel_relaxed(ip ^ mask, mapbase + SA1111_INTPOL0); in sa1111_retrigger_irq()
292 writel_relaxed(ip, mapbase + SA1111_INTPOL0); in sa1111_retrigger_irq()
323 writel_relaxed(ip, mapbase + SA1111_INTPOL0); in sa1111_type_irq()
324 writel_relaxed(ip, mapbase + SA1111_WAKEPOL0); in sa1111_type_irq()
340 writel_relaxed(we, mapbase + SA1111_WAKEEN0); in sa1111_wake_irq()
398 writel_relaxed(0, irqbase + SA1111_INTEN0); in sa1111_setup_irq()
399 writel_relaxed(0, irqbase + SA1111_INTEN1); in sa1111_setup_irq()
[all …]
/arch/arm/mach-imx/
Dgpc.c36 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | in imx_gpc_set_arm_power_up_timing()
42 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | in imx_gpc_set_arm_power_down_timing()
48 writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN); in imx_gpc_set_arm_power_in_lpm()
59 writel_relaxed(val, gpc_base + GPC_CNTR); in imx_gpc_set_l2_mem_power_in_lpm()
73 writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4); in imx_gpc_pre_suspend()
86 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); in imx_gpc_post_resume()
112 writel_relaxed(~0, reg_imr1 + i * 4); in imx_gpc_mask_all()
122 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); in imx_gpc_restore_all()
133 writel_relaxed(val, reg); in imx_gpc_hwirq_unmask()
144 writel_relaxed(val, reg); in imx_gpc_hwirq_mask()
[all …]
Dsrc.c68 writel_relaxed(val, src_base + SRC_SCR); in imx_src_reset_module()
87 writel_relaxed(enable, gpc_base + offset); in imx_gpcv2_set_m_core_pgc()
108 writel_relaxed(val, gpc_base + reg); in imx_gpcv2_set_core1_pdn_pup_by_software()
116 writel_relaxed(val, gpc_base + reg); in imx_gpcv2_set_core1_pdn_pup_by_software()
135 writel_relaxed(val, src_base + SRC_A7RCR1); in imx_enable_cpu()
141 writel_relaxed(val, src_base + SRC_SCR); in imx_enable_cpu()
149 writel_relaxed(__pa_symbol(jump_addr), in imx_set_cpu_jump()
162 writel_relaxed(arg, src_base + SRC_GPR1(gpr_v2) + cpu * 8 + 4); in imx_set_cpu_arg()
183 writel_relaxed(val, src_base + SRC_SCR); in imx_src_init()
Dmach-imx51.c66 writel_relaxed(0x00000203, m4if_base + 0x40); in imx51_m4if_setup()
67 writel_relaxed(0x00000000, m4if_base + 0x44); in imx51_m4if_setup()
68 writel_relaxed(0x00120125, m4if_base + 0x9c); in imx51_m4if_setup()
69 writel_relaxed(0x001901A3, m4if_base + 0x48); in imx51_m4if_setup()
/arch/arm/mach-pxa/
Dreset.c77 writel_relaxed(OWER_WME, OWER); in do_hw_reset()
78 writel_relaxed(OSSR_M3, OSSR); in do_hw_reset()
80 writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3); in do_hw_reset()
86 writel_relaxed(MDREFR_SLFRSH, MDREFR); in do_hw_reset()
/arch/arm/mach-mvebu/
Dkirkwood-pm.c25 writel_relaxed(~0, memory_pm_ctrl); in kirkwood_low_power()
28 writel_relaxed(0x7, ddr_operation_base); in kirkwood_low_power()
37 writel_relaxed(mem_pm_ctrl, memory_pm_ctrl); in kirkwood_low_power()
/arch/arm/mach-aspeed/
Dplatsmp.c25 writel_relaxed(0, base + BOOT_ADDR); in aspeed_g6_boot_secondary()
26 writel_relaxed(__pa_symbol(secondary_startup_arm), base + BOOT_ADDR); in aspeed_g6_boot_secondary()
27 writel_relaxed((0xABBAAB00 | (cpu & 0xff)), base + BOOT_SIG); in aspeed_g6_boot_secondary()
/arch/arm/mach-exynos/
Dfirmware.c40 writel_relaxed(__pa_symbol(exynos_cpu_resume_ns), in exynos_do_idle()
42 writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20); in exynos_do_idle()
91 writel_relaxed(boot_addr, boot_reg); in exynos_set_cpu_boot_addr()
243 writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4); in exynos_set_boot_flag()
252 writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4); in exynos_clear_boot_flag()
/arch/arm/mach-vexpress/
Ddcscb.c49 writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cpu_powerup()
65 writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cluster_powerup()
78 writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cpu_powerdown_prepare()
90 writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cluster_powerdown_prepare()
/arch/arm/mach-spear/
Dspear13xx.c39 writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL); in spear13xx_l2x0_init()
45 writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL); in spear13xx_l2x0_init()
46 writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL); in spear13xx_l2x0_init()
/arch/arm/mach-s3c/
Dpm-common.c52 writel_relaxed(ptr->val, ptr->reg); in s3c_pm_do_restore()
72 writel_relaxed(ptr->val, ptr->reg); in s3c_pm_do_restore_core()
/arch/arm/mm/
Dcache-l2x0.c72 writel_relaxed(val, base + reg); in l2c_write_sec()
87 writel_relaxed(l2x0_way_mask, reg); in __l2c_op_way()
96 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE + in l2c_unlock()
98 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE + in l2c_unlock()
125 writel_relaxed(0, base + sync_reg_offset); in l2c_enable()
175 writel_relaxed(0, base + sync_reg_offset); in __l2c210_cache_sync()
182 writel_relaxed(start, reg); in __l2c210_op_pa_range()
193 writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA); in l2c210_inv_range()
199 writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA); in l2c210_inv_range()
270 writel_relaxed(0, base + L2X0_CACHE_SYNC); in __l2c220_cache_sync()
[all …]
Dcache-uniphier.c98 writel_relaxed(UNIPHIER_SSCOPE_CM_SYNC, in __uniphier_cache_sync()
145 writel_relaxed(UNIPHIER_SSCOLPQS_EF, data->op_base + UNIPHIER_SSCOLPQS); in __uniphier_cache_maint_common()
149 writel_relaxed(UNIPHIER_SSCOQM_CE | operation, in __uniphier_cache_maint_common()
154 writel_relaxed(start, data->op_base + UNIPHIER_SSCOQAD); in __uniphier_cache_maint_common()
155 writel_relaxed(size, data->op_base + UNIPHIER_SSCOQSZ); in __uniphier_cache_maint_common()
224 writel_relaxed(val, data->ctrl_base + UNIPHIER_SSCC); in __uniphier_cache_enable()
233 writel_relaxed(data->way_mask, data->way_ctrl_base + 4 * cpu); in __uniphier_cache_set_active_ways()
/arch/arm/mach-bcm/
Dbcm_kona_smc.c148 writel_relaxed(data->arg0, args++); in __bcm_kona_smc()
149 writel_relaxed(data->arg1, args++); in __bcm_kona_smc()
150 writel_relaxed(data->arg2, args++); in __bcm_kona_smc()
/arch/arm/mach-highbank/
Dsysregs.h33 writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu)); in highbank_set_core_pwr()
42 writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu)); in highbank_clear_core_pwr()

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