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Searched refs:xl (Results 1 – 5 of 5) sorted by relevance

/arch/arm/lib/
Dmuldi3.S15 #define xl r1 macro
19 #define xl r0 macro
29 mla xh, xl, yh, xh
30 mov ip, xl, lsr #16
32 bic xl, xl, ip, lsl #16
35 mul yh, xl, yh
36 mul xl, yl, xl
38 adds xl, xl, yh, lsl #16
40 adds xl, xl, ip, lsl #16
Ddiv64.S18 #define xl r1 macro
22 #define xl r0 macro
96 cmpeq xl, r4
97 movlo xh, xl
104 4: movs xl, xl, lsl #1
118 cmp xl, #0
125 clz xh, xl @ we know xh is zero here so...
127 mov xl, xl, lsl xh
132 7: movs xl, xl, lsl #1
178 mov yl, xl, lsr ip
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Ducmpdi2.S15 #define xl r1 macro
19 #define xl r0 macro
28 cmpeq xl, yl
41 cmpeq xl, yl
/arch/alpha/kernel/
Dsys_sio.c483 ALIAS_MV(xl)
/arch/x86/events/intel/
Dcore.c3224 struct intel_excl_states *xl; in intel_start_scheduling() local
3239 xl = &excl_cntrs->states[tid]; in intel_start_scheduling()
3241 xl->sched_started = true; in intel_start_scheduling()
3254 struct intel_excl_states *xl; in intel_commit_scheduling() local
3266 xl = &excl_cntrs->states[tid]; in intel_commit_scheduling()
3271 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; in intel_commit_scheduling()
3273 xl->state[cntr] = INTEL_EXCL_SHARED; in intel_commit_scheduling()
3280 struct intel_excl_states *xl; in intel_stop_scheduling() local
3294 xl = &excl_cntrs->states[tid]; in intel_stop_scheduling()
3296 xl->sched_started = false; in intel_stop_scheduling()
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