| /drivers/gpu/drm/amd/include/asic_reg/smu/ |
| D | smu_8_0_enum.h | 959 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
|
| D | smu_7_1_0_enum.h | 1118 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
|
| D | smu_7_1_2_enum.h | 1137 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
|
| D | smu_7_1_3_enum.h | 1173 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
|
| D | smu_7_1_1_enum.h | 1119 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
|
| /drivers/gpu/drm/amd/include/asic_reg/bif/ |
| D | bif_5_1_enum.h | 959 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
|
| D | bif_5_0_enum.h | 1089 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
|
| /drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| D | gmc_8_2_enum.h | 959 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
|
| D | gmc_8_1_enum.h | 1089 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
|
| /drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_6_0_enum.h | 972 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
|
| D | uvd_5_0_enum.h | 1102 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
|
| /drivers/gpu/drm/amd/include/asic_reg/dce/ |
| D | dce_8_0_enum.h | 1044 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
|
| D | dce_10_0_enum.h | 1664 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
|
| /drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v8_0.c | 2245 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2273 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2277 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2843 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2848 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
3228 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
3232 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
3405 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
3409 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
|
| D | gfx_v7_0.c | 1186 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v7_0_tiling_mode_table_init()
1190 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v7_0_tiling_mode_table_init()
1547 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v7_0_tiling_mode_table_init()
1551 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v7_0_tiling_mode_table_init()
|
| D | gfx_v6_0.c | 811 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v6_0_tiling_mode_table_init()
994 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v6_0_tiling_mode_table_init()
1002 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v6_0_tiling_mode_table_init()
|
| D | sid.h | 1205 # define ADDR_SURF_BANK_WIDTH_2 1 macro
|
| /drivers/gpu/drm/amd/include/asic_reg/oss/ |
| D | oss_2_4_enum.h | 1254 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
|
| D | oss_3_0_enum.h | 1388 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
|
| D | oss_3_0_1_enum.h | 1355 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
|
| /drivers/gpu/drm/radeon/ |
| D | sid.h | 1208 # define ADDR_SURF_BANK_WIDTH_2 1 macro
|
| D | cik.c | 2832 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
2836 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
2947 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
2951 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
2983 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
2987 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
|
| D | cikd.h | 1262 # define ADDR_SURF_BANK_WIDTH_2 1 macro
|
| D | evergreend.h | 2219 # define ADDR_SURF_BANK_WIDTH_2 1 macro
|
| D | si.c | 2682 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in si_tiling_mode_table_init()
2897 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in si_tiling_mode_table_init()
|