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Searched refs:AMDGPU_UVD_FIRMWARE_OFFSET (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Damdgpu_uvd.h32 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 macro
38 8) - AMDGPU_UVD_FIRMWARE_OFFSET)
Duvd_v4_2.c575 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; in uvd_v4_2_mc_resume()
Duvd_v3_1.c246 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; in uvd_v3_1_mc_resume()
Dvcn_v2_5.c417 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_5_mc_resume()
483 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1220 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_5_sriov_start()
Duvd_v5_0.c287 offset = AMDGPU_UVD_FIRMWARE_OFFSET; in uvd_v5_0_mc_resume()
Dvcn_v3_0.c482 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v3_0_mc_resume()
547 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1373 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v3_0_start_sriov()
Dvcn_v1_0.c321 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v1_0_mc_resume_spg_mode()
391 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
Dvcn_v2_0.c351 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_0_mc_resume()
419 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
Duvd_v7_0.c703 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in uvd_v7_0_mc_resume()
845 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in uvd_v7_0_sriov_start()
Duvd_v6_0.c620 offset = AMDGPU_UVD_FIRMWARE_OFFSET; in uvd_v6_0_mc_resume()