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Searched refs:BIT2 (Results 1 – 25 of 38) sorted by relevance

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/drivers/scsi/
Ddc395x.h74 #define BIT2 0x00000004 macro
81 #define FORMATING_MEDIA BIT2
87 #define ASPI_SUPPORT BIT2
123 #define RESET_DONE BIT2
131 #define OVER_RUN BIT2
141 #define RESET_DEV0 BIT2
167 #define WIDE_NEGO_ENABLE BIT2
594 #define RST_SCSI_BUS BIT2
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h130 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
147 #define RCR_AM BIT2
203 #define SCR_TxEncEnable BIT2
226 #define IMR_VIDOK BIT2
233 #define TPPoll_VIQ BIT2
273 #define AcmHw_ViqEn BIT2
281 #define AcmFw_VoqStatus BIT2
334 #define BW_OPMODE_20MHZ BIT2
363 #define RRSR_5_5M BIT2
/drivers/staging/rtl8723bs/include/
Dhal_com_reg.h610 #define RRSR_5_5M BIT2
635 #define HAL92C_WOL_DISASSOC_EVENT BIT2
700 #define BW_OPMODE_20MHZ BIT2
733 #define WOW_MAGIC BIT2 /* Magic packet */
774 #define IMR_VIDOK BIT2 /* AC_VI DMA OK Interrupt */
822 #define PHIMR_VODOK BIT2 /* AC_VO DMA Interrupt */
873 #define UHIMR_VODOK BIT2 /* AC_VO DMA Interrupt */
927 #define IMR_VODOK_88E BIT2 /* AC_VO DMA OK */
985 #define StopBE BIT2
1022 #define RCR_AM BIT2 /* Accept multicast packet */
[all …]
Drtw_ht.h66 #define LDPC_HT_TEST_TX_ENABLE BIT2
71 #define STBC_HT_TEST_TX_ENABLE BIT2
76 #define BEAMFORMING_HT_BEAMFORMER_TEST BIT2 /* Transmiting Beamforming no matter the target suppo…
Dhal_pwr_seq.h48 …AB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW …
105 …K, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1…
183 …_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/ \
208 …MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/…
210 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/…
Drtl8723b_spec.h212 #define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */
Dosdep_service.h19 #define BIT2 0x00000004 macro
/drivers/video/fbdev/via/
Ddvi.c335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
Dlcd.c345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
520 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
561 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
744 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
Dshare.h16 #define BIT2 0x04 macro
/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dpwrseq.h26 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
130 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
199 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
205 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
386 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
523 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
/drivers/staging/rtl8723bs/hal/
DHalHWImg8723B_MAC.c20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ in CheckPositive()
60 if ((cond1 & BIT2) != 0) /* ALNA */ in CheckPositive()
DHalHWImg8723B_RF.c20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ in CheckPositive()
66 if ((cond1 & BIT2) != 0) /* ALNA */ in CheckPositive()
DHalHWImg8723B_BB.c20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ in CheckPositive()
61 if ((cond1 & BIT2) != 0) /* ALNA */ in CheckPositive()
DHalBtc8723b2Ant.h13 #define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
DHalBtc8723b1Ant.h13 #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h33 #define BIT2 0x00000004 macro
Dhalbtcoutsrc.h89 #define INTF_NOTIFY BIT2
94 #define ALGO_BT_MONITOR BIT2
106 #define WIFI_HS_CONNECTED BIT2
Dhalbtc8821a2ant.h13 #define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT2
Dhalbtc8192e2ant.h12 #define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT2
Dhalbtc8821a1ant.h13 #define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT2
Dhalbtc8723b2ant.h15 #define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
/drivers/char/pcmcia/
Dsynclink_cs.c301 #define IRQ_DCD BIT2 // carrier detect status change
308 #define CEC BIT2 // command executing
313 #define PVR_RI BIT2
688 while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) { in wait_command_complete()
1190 if (gis & (BIT3 | BIT2)) in mgslpc_isr()
1237 if (pis & BIT2) in mgslpc_isr()
2915 val |= BIT2; in enable_auxclk()
2987 val = read_reg(info, CHA + CCR1) | (BIT2 | BIT1 | BIT0); in loopback_enable()
3058 val |= BIT2; in hdlc_mode()
3081 val |= BIT4 | BIT2; in hdlc_mode()
[all …]
/drivers/tty/
Dsynclink_gt.c193 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
1940 if (status & BIT2) { in cts_change()
2210 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in isr_txeom()
3828 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); in enable_loopback()
3877 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ in rx_stop()
3902 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ in rx_start()
3924 wr_reg32(info, RDCSR, (BIT2 + BIT0)); in rx_start()
3927 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); in rx_start()
3944 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); in tx_start()
3973 wr_reg32(info, TDCSR, BIT2 + BIT0); in tx_start()
[all …]
/drivers/staging/rtl8192e/
Drtl819x_Qos.h12 #define BIT2 0x00000004 macro

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