Home
last modified time | relevance | path

Searched refs:BIT7 (Results 1 – 25 of 36) sorted by relevance

12

/drivers/staging/rtl8723bs/include/
Dhal_pwr_seq.h53 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7…
94 …WR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspen…
114 …WR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspen…
129 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1…
134 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7…
162 …SK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x10…
163 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] …
192 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF s…
201 …MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF s…
211 …PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW in…
Dhal_com_reg.h563 #define HSIMR_PDN_INT_EN BIT7
572 #define HSISR_PDNINT BIT7
615 #define RRSR_18M BIT7
769 #define IMR_TBDOK BIT7 /* Transmit Beacon OK interrupt */
817 #define PHIMR_HIGHDOK BIT7 /* High Queue DMA OK Interrupt */
868 #define UHIMR_HIGHDOK BIT7 /* High Queue DMA OK Interrupt */
922 #define IMR_HIGHDOK_88E BIT7 /* High Queue DMA OK */
1016 #define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet (Rx beacon, probe rsp) */
1546 #define SDIO_HIMR_TXBCNERR_MSK BIT7
1572 #define SDIO_HISR_TXBCNERR BIT7
[all …]
Drtl8723b_spec.h207 #define IMR_HIGHDOK_8723B BIT7 /* High Queue DMA OK */
Dosdep_service.h24 #define BIT7 0x00000080 macro
/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dpwrseq.h32 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
93 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
152 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
213 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
218 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
282 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
285 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
401 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
499 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
540 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
[all …]
/drivers/video/fbdev/via/
Dvia_utility.c138 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7); in viafb_set_gamma_table()
148 viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7); in viafb_set_gamma_table()
193 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7); in viafb_get_gamma_table()
203 viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7); in viafb_get_gamma_table()
Dlcd.c376 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6); in load_lcd_scaling()
388 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7); in load_lcd_scaling()
609 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
618 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
625 viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7); in integrated_lvds_disable()
637 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
661 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
670 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
680 viafb_write_reg_mask(CRD2, VIACR, 0, BIT7); in integrated_lvds_enable()
692 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
[all …]
Ddvi.c55 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
62 BIT5 + BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
453 viafb_write_reg_mask(CR91, VIACR, 0, BIT7); in viafb_dvi_enable()
Dhw.c466 viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7); in viafb_lock_crt()
471 viafb_write_reg_mask(CR11, VIACR, 0, BIT7); in viafb_unlock_crt()
945 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7); in load_fix_bit_crtc_reg()
1669 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); in viafb_init_dac()
1676 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); in viafb_init_dac()
2034 viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7); in enable_second_display_channel()
2042 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7); in disable_second_display_channel()
Dshare.h21 #define BIT7 0x80 macro
/drivers/staging/rtl8723bs/hal/
Dodm_NoiseMonitor.c105 reg_c50 &= ~BIT7; in odm_InbandNoise_Monitor_NSeries()
111 reg_c58 &= ~BIT7; in odm_InbandNoise_Monitor_NSeries()
DHalHWImg8723B_MAC.c18 ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */ in CheckPositive()
DHalBtc8723b2Ant.h8 #define BT_INFO_8723B_2ANT_B_FTP BIT7
DHalBtc8723b1Ant.h8 #define BT_INFO_8723B_1ANT_B_FTP BIT7
DHalHWImg8723B_RF.c18 ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */ in CheckPositive()
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h221 #define IMR_COMDOK BIT7
238 #define TPPoll_HQ BIT7
368 #define RRSR_18M BIT7
/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h38 #define BIT7 0x00000080 macro
Dhalbtc8821a2ant.h8 #define BT_INFO_8821A_2ANT_B_FTP BIT7
Dhalbtc8192e2ant.h7 #define BT_INFO_8192E_2ANT_B_FTP BIT7
Dhalbtc8821a1ant.h8 #define BT_INFO_8821A_1ANT_B_FTP BIT7
Dhalbtc8723b2ant.h10 #define BT_INFO_8723B_2ANT_B_FTP BIT7
Dhalbtc8723b1ant.h7 #define BT_INFO_8723B_1ANT_B_FTP BIT7
/drivers/scsi/
Ddc395x.h69 #define BIT7 0x00000080 macro
137 #define DATAOUT BIT7
/drivers/staging/rtl8192e/
Drtl819x_Qos.h17 #define BIT7 0x00000080 macro
/drivers/char/pcmcia/
Dsynclink_cs.c298 #define IRQ_RXEOM BIT7 // receive message end
676 #define CMD_RXFIFO BIT7 // release current rx FIFO
925 if (status & (BIT7 + BIT6)) { in rx_ready_async()
926 if (status & BIT7) in rx_ready_async()
937 if (status & BIT7) in rx_ready_async()
1233 if (gis & BIT7) { in mgslpc_isr()
1468 info->read_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
1470 info->ignore_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
3153 val |= BIT7 | BIT6; in hdlc_mode()
3565 if (read_reg(info, CHB + VSTR) & BIT7) in get_signals()
[all …]

12