Home
last modified time | relevance | path

Searched refs:CONTROL (Results 1 – 25 of 50) sorted by relevance

12

/drivers/clocksource/
Dtimer-digicolor.c51 #define CONTROL(t) ((t)*8) macro
75 writeb(CONTROL_DISABLE, dt->base + CONTROL(dt->timer_id)); in dc_timer_disable()
81 writeb(CONTROL_ENABLE | mode, dt->base + CONTROL(dt->timer_id)); in dc_timer_enable()
183 writeb(CONTROL_DISABLE, dc_timer_dev.base + CONTROL(TIMER_B)); in digicolor_timer_init()
185 writeb(CONTROL_ENABLE, dc_timer_dev.base + CONTROL(TIMER_B)); in digicolor_timer_init()
/drivers/parport/
Dparport_gsc.c84 s->u.pc.ctr = parport_readb (CONTROL (p)); in parport_gsc_save_state()
89 parport_writeb (s->u.pc.ctr, CONTROL (p)); in parport_gsc_restore_state()
148 parport_writeb (w, CONTROL (pb)); in parport_SPP_supported()
155 r = parport_readb (CONTROL (pb)); in parport_SPP_supported()
158 parport_writeb (w, CONTROL (pb)); in parport_SPP_supported()
159 r = parport_readb (CONTROL (pb)); in parport_SPP_supported()
160 parport_writeb (0xc, CONTROL (pb)); in parport_SPP_supported()
Dparport_gsc.h47 #define CONTROL(p) ((p)->base + 0x2) macro
103 parport_writeb (ctr, CONTROL (p)); in __parport_gsc_frob_control()
Dparport_pc.c252 outb(c, CONTROL(p)); in parport_pc_restore_state()
1411 outb(w, CONTROL(pb)); in parport_SPP_supported()
1418 r = inb(CONTROL(pb)); in parport_SPP_supported()
1421 outb(w, CONTROL(pb)); in parport_SPP_supported()
1422 r = inb(CONTROL(pb)); in parport_SPP_supported()
1423 outb(0xc, CONTROL(pb)); in parport_SPP_supported()
1482 outb(r, CONTROL(pb)); in parport_ECR_present()
1484 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */ in parport_ECR_present()
1486 r = inb(CONTROL(pb)); in parport_ECR_present()
1499 outb(0xc, CONTROL(pb)); in parport_ECR_present()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_optc.c107 REG_UPDATE(CONTROL, in optc31_enable_crtc()
134 REG_UPDATE(CONTROL, in optc31_disable_crtc()
153 REG_UPDATE(CONTROL, in optc31_immediate_disable_crtc()
/drivers/bluetooth/
Dbt3c_cs.c113 #define CONTROL 4 macro
349 iir = inb(iobase + CONTROL); in bt3c_interrupt()
370 outb(iir, iobase + CONTROL); in bt3c_interrupt()
524 outb(inb(iobase + CONTROL) | 0x40, iobase + CONTROL); in bt3c_load_firmware()
/drivers/watchdog/
Dmachzwd.c52 #define CONTROL 0x10 /* 16 */ macro
155 return zf_readw(CONTROL); in zf_get_control()
160 zf_writew(CONTROL, new); in zf_set_control()
/drivers/media/usb/uvc/
Duvc_ctrl.c886 uvc_dbg(chain->dev, CONTROL, "Control 0x%08x not found\n", in uvc_find_control()
1946 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info()
1959 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info()
1967 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info()
1997 uvc_dbg(dev, CONTROL, in uvc_ctrl_init_xu_ctrl()
2028 uvc_dbg(chain->dev, CONTROL, "Extension unit %u not found\n", in uvc_xu_ctrl_query()
2044 uvc_dbg(chain->dev, CONTROL, "Control %pUl/%u not found\n", in uvc_xu_ctrl_query()
2193 uvc_dbg(dev, CONTROL, "Added control %pUl/%u to device %s entity %u\n", in uvc_ctrl_add_info()
2241 uvc_dbg(chain->dev, CONTROL, "Adding mapping '%s' to control %pUl/%u\n", in __uvc_ctrl_add_mapping()
2259 uvc_dbg(dev, CONTROL, in uvc_ctrl_add_mapping()
[all …]
/drivers/hwmon/
Dadt7475.c30 #define CONTROL 3 macro
788 data->pwm[CONTROL][sattr->index] = in pwm_store()
795 if (((data->pwm[CONTROL][sattr->index] >> 5) & 7) != 7) { in pwm_store()
906 data->pwm[CONTROL][index] &= ~0xE0; in hw_set_pwm()
907 data->pwm[CONTROL][index] |= (val & 7) << 5; in hw_set_pwm()
910 data->pwm[CONTROL][index]); in hw_set_pwm()
1751 data->pwm[CONTROL][index] = adt7475_read(PWM_CONFIG_REG(index)); in adt7475_read_pwm()
1757 v = (data->pwm[CONTROL][index] >> 5) & 7; in adt7475_read_pwm()
1770 data->pwm[CONTROL][index] &= ~0xE0; in adt7475_read_pwm()
1771 data->pwm[CONTROL][index] |= (7 << 5); in adt7475_read_pwm()
[all …]
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_opp.h78 SRI(CONTROL, FMT_MEMORY, id)
82 SRI(CONTROL, FMT_MEMORY, id)
295 uint32_t CONTROL; member
Ddce_opp.c589 REG_GET(CONTROL, in program_formatter_420_memory()
596 REG_UPDATE(CONTROL, in program_formatter_420_memory()
Ddce_hwseq.h659 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\
660 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\
661 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\
662 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh)
683 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
/drivers/net/ethernet/smsc/
Dsmc9194.c338 outw( inw( ioaddr + CONTROL ) | CTL_AUTO_RELEASE , ioaddr + CONTROL ); in smc_reset()
398 outw( inw( ioaddr + CONTROL ), CTL_POWERDOWN, ioaddr + CONTROL ); in smc_shutdown()
Dsmc91c92_cs.c191 #define CONTROL 12 macro
550 outw((CTL_RELOAD | CTL_EE_SELECT), ioaddr + CONTROL); in mot_setup()
554 wait = ((CTL_RELOAD | CTL_STORE) & inw(ioaddr + CONTROL)); in mot_setup()
772 outw(0, ioaddr + CONTROL); in check_sig()
1102 outw(CTL_POWERDOWN, ioaddr + CONTROL ); in smc_close()
1333 outw(CTL_AUTO_RELEASE | 0x0000, ioaddr + CONTROL); in smc_eph_irq()
1335 ioaddr + CONTROL); in smc_eph_irq()
1661 ioaddr + CONTROL); in smc_reset()
Dsmc9194.h104 #define CONTROL 12 macro
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_optc.c277 REG_UPDATE(CONTROL, in optc1_program_timing()
368 REG_UPDATE_2(CONTROL, in optc1_set_vtg_params()
372 REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init); in optc1_set_vtg_params()
517 REG_UPDATE(CONTROL, in optc1_enable_crtc()
545 REG_UPDATE(CONTROL, in optc1_disable_crtc()
Ddcn10_optc.h78 SRI(CONTROL, VTG, inst),\
156 uint32_t CONTROL; member
/drivers/scsi/
Daha1542.h29 #define CONTROL(base) STATUS(base) macro
Daha1542.c78 outb(IRST, CONTROL(base)); in aha1542_intr_reset()
221 outb(SRST | IRST /*|SCRST */ , CONTROL(sh->io_port)); in aha1542_test_port()
255 outb(IRST, CONTROL(sh->io_port)); in aha1542_test_port()
941 outb(reset_cmd, CONTROL(cmd->device->host->io_port)); in aha1542_reset()
/drivers/i3c/master/mipi-i3c-hci/
Ddma.c202 rhs_reg_write(CONTROL, 0); in hci_dma_cleanup()
217 regval = rhs_reg_read(CONTROL); in hci_dma_init()
332 rhs_reg_write(CONTROL, regval); in hci_dma_init()
/drivers/net/ethernet/marvell/prestera/
Dprestera_devlink.c135 DEVLINK_TRAP_GENERIC(CONTROL, _action, _id, \
140 DEVLINK_TRAP_DRIVER(CONTROL, TRAP, DEVLINK_PRESTERA_TRAP_ID_##_id, \
/drivers/hid/
Dhid-roccat-lua.c95 LUA_BIN_ATTRIBUTE_RW(control, CONTROL) in LUA_BIN_ATTRIBUTE_RW() argument
/drivers/phy/ti/
DKconfig53 tristate "OMAP CONTROL PHY Driver"
/drivers/video/fbdev/omap2/omapfb/dss/
Ddss.c132 SR(CONTROL); in dss_save_context()
152 RR(CONTROL); in dss_restore_context()
/drivers/usb/gadget/udc/
Dpxa27x_udc.h260 #define USB_EP_CTRL USB_EP_DEF(0, "ep0", 0, CONTROL, EP0_FIFO_SIZE, \

12