/drivers/clocksource/ |
D | timer-digicolor.c | 51 #define CONTROL(t) ((t)*8) macro 75 writeb(CONTROL_DISABLE, dt->base + CONTROL(dt->timer_id)); in dc_timer_disable() 81 writeb(CONTROL_ENABLE | mode, dt->base + CONTROL(dt->timer_id)); in dc_timer_enable() 183 writeb(CONTROL_DISABLE, dc_timer_dev.base + CONTROL(TIMER_B)); in digicolor_timer_init() 185 writeb(CONTROL_ENABLE, dc_timer_dev.base + CONTROL(TIMER_B)); in digicolor_timer_init()
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/drivers/parport/ |
D | parport_gsc.c | 84 s->u.pc.ctr = parport_readb (CONTROL (p)); in parport_gsc_save_state() 89 parport_writeb (s->u.pc.ctr, CONTROL (p)); in parport_gsc_restore_state() 148 parport_writeb (w, CONTROL (pb)); in parport_SPP_supported() 155 r = parport_readb (CONTROL (pb)); in parport_SPP_supported() 158 parport_writeb (w, CONTROL (pb)); in parport_SPP_supported() 159 r = parport_readb (CONTROL (pb)); in parport_SPP_supported() 160 parport_writeb (0xc, CONTROL (pb)); in parport_SPP_supported()
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D | parport_gsc.h | 47 #define CONTROL(p) ((p)->base + 0x2) macro 103 parport_writeb (ctr, CONTROL (p)); in __parport_gsc_frob_control()
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D | parport_pc.c | 252 outb(c, CONTROL(p)); in parport_pc_restore_state() 1411 outb(w, CONTROL(pb)); in parport_SPP_supported() 1418 r = inb(CONTROL(pb)); in parport_SPP_supported() 1421 outb(w, CONTROL(pb)); in parport_SPP_supported() 1422 r = inb(CONTROL(pb)); in parport_SPP_supported() 1423 outb(0xc, CONTROL(pb)); in parport_SPP_supported() 1482 outb(r, CONTROL(pb)); in parport_ECR_present() 1484 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */ in parport_ECR_present() 1486 r = inb(CONTROL(pb)); in parport_ECR_present() 1499 outb(0xc, CONTROL(pb)); in parport_ECR_present() [all …]
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/drivers/gpu/drm/amd/display/dc/dcn31/ |
D | dcn31_optc.c | 107 REG_UPDATE(CONTROL, in optc31_enable_crtc() 134 REG_UPDATE(CONTROL, in optc31_disable_crtc() 153 REG_UPDATE(CONTROL, in optc31_immediate_disable_crtc()
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/drivers/bluetooth/ |
D | bt3c_cs.c | 113 #define CONTROL 4 macro 349 iir = inb(iobase + CONTROL); in bt3c_interrupt() 370 outb(iir, iobase + CONTROL); in bt3c_interrupt() 524 outb(inb(iobase + CONTROL) | 0x40, iobase + CONTROL); in bt3c_load_firmware()
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/drivers/watchdog/ |
D | machzwd.c | 52 #define CONTROL 0x10 /* 16 */ macro 155 return zf_readw(CONTROL); in zf_get_control() 160 zf_writew(CONTROL, new); in zf_set_control()
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/drivers/media/usb/uvc/ |
D | uvc_ctrl.c | 886 uvc_dbg(chain->dev, CONTROL, "Control 0x%08x not found\n", in uvc_find_control() 1946 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info() 1959 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info() 1967 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info() 1997 uvc_dbg(dev, CONTROL, in uvc_ctrl_init_xu_ctrl() 2028 uvc_dbg(chain->dev, CONTROL, "Extension unit %u not found\n", in uvc_xu_ctrl_query() 2044 uvc_dbg(chain->dev, CONTROL, "Control %pUl/%u not found\n", in uvc_xu_ctrl_query() 2193 uvc_dbg(dev, CONTROL, "Added control %pUl/%u to device %s entity %u\n", in uvc_ctrl_add_info() 2241 uvc_dbg(chain->dev, CONTROL, "Adding mapping '%s' to control %pUl/%u\n", in __uvc_ctrl_add_mapping() 2259 uvc_dbg(dev, CONTROL, in uvc_ctrl_add_mapping() [all …]
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/drivers/hwmon/ |
D | adt7475.c | 30 #define CONTROL 3 macro 788 data->pwm[CONTROL][sattr->index] = in pwm_store() 795 if (((data->pwm[CONTROL][sattr->index] >> 5) & 7) != 7) { in pwm_store() 906 data->pwm[CONTROL][index] &= ~0xE0; in hw_set_pwm() 907 data->pwm[CONTROL][index] |= (val & 7) << 5; in hw_set_pwm() 910 data->pwm[CONTROL][index]); in hw_set_pwm() 1751 data->pwm[CONTROL][index] = adt7475_read(PWM_CONFIG_REG(index)); in adt7475_read_pwm() 1757 v = (data->pwm[CONTROL][index] >> 5) & 7; in adt7475_read_pwm() 1770 data->pwm[CONTROL][index] &= ~0xE0; in adt7475_read_pwm() 1771 data->pwm[CONTROL][index] |= (7 << 5); in adt7475_read_pwm() [all …]
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/drivers/gpu/drm/amd/display/dc/dce/ |
D | dce_opp.h | 78 SRI(CONTROL, FMT_MEMORY, id) 82 SRI(CONTROL, FMT_MEMORY, id) 295 uint32_t CONTROL; member
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D | dce_opp.c | 589 REG_GET(CONTROL, in program_formatter_420_memory() 596 REG_UPDATE(CONTROL, in program_formatter_420_memory()
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D | dce_hwseq.h | 659 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ 660 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ 661 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ 662 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) 683 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
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/drivers/net/ethernet/smsc/ |
D | smc9194.c | 338 outw( inw( ioaddr + CONTROL ) | CTL_AUTO_RELEASE , ioaddr + CONTROL ); in smc_reset() 398 outw( inw( ioaddr + CONTROL ), CTL_POWERDOWN, ioaddr + CONTROL ); in smc_shutdown()
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D | smc91c92_cs.c | 191 #define CONTROL 12 macro 550 outw((CTL_RELOAD | CTL_EE_SELECT), ioaddr + CONTROL); in mot_setup() 554 wait = ((CTL_RELOAD | CTL_STORE) & inw(ioaddr + CONTROL)); in mot_setup() 772 outw(0, ioaddr + CONTROL); in check_sig() 1102 outw(CTL_POWERDOWN, ioaddr + CONTROL ); in smc_close() 1333 outw(CTL_AUTO_RELEASE | 0x0000, ioaddr + CONTROL); in smc_eph_irq() 1335 ioaddr + CONTROL); in smc_eph_irq() 1661 ioaddr + CONTROL); in smc_reset()
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D | smc9194.h | 104 #define CONTROL 12 macro
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/drivers/gpu/drm/amd/display/dc/dcn10/ |
D | dcn10_optc.c | 277 REG_UPDATE(CONTROL, in optc1_program_timing() 368 REG_UPDATE_2(CONTROL, in optc1_set_vtg_params() 372 REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init); in optc1_set_vtg_params() 517 REG_UPDATE(CONTROL, in optc1_enable_crtc() 545 REG_UPDATE(CONTROL, in optc1_disable_crtc()
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D | dcn10_optc.h | 78 SRI(CONTROL, VTG, inst),\ 156 uint32_t CONTROL; member
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/drivers/scsi/ |
D | aha1542.h | 29 #define CONTROL(base) STATUS(base) macro
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D | aha1542.c | 78 outb(IRST, CONTROL(base)); in aha1542_intr_reset() 221 outb(SRST | IRST /*|SCRST */ , CONTROL(sh->io_port)); in aha1542_test_port() 255 outb(IRST, CONTROL(sh->io_port)); in aha1542_test_port() 941 outb(reset_cmd, CONTROL(cmd->device->host->io_port)); in aha1542_reset()
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/drivers/i3c/master/mipi-i3c-hci/ |
D | dma.c | 202 rhs_reg_write(CONTROL, 0); in hci_dma_cleanup() 217 regval = rhs_reg_read(CONTROL); in hci_dma_init() 332 rhs_reg_write(CONTROL, regval); in hci_dma_init()
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/drivers/net/ethernet/marvell/prestera/ |
D | prestera_devlink.c | 135 DEVLINK_TRAP_GENERIC(CONTROL, _action, _id, \ 140 DEVLINK_TRAP_DRIVER(CONTROL, TRAP, DEVLINK_PRESTERA_TRAP_ID_##_id, \
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/drivers/hid/ |
D | hid-roccat-lua.c | 95 LUA_BIN_ATTRIBUTE_RW(control, CONTROL) in LUA_BIN_ATTRIBUTE_RW() argument
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/drivers/phy/ti/ |
D | Kconfig | 53 tristate "OMAP CONTROL PHY Driver"
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/drivers/video/fbdev/omap2/omapfb/dss/ |
D | dss.c | 132 SR(CONTROL); in dss_save_context() 152 RR(CONTROL); in dss_restore_context()
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/drivers/usb/gadget/udc/ |
D | pxa27x_udc.h | 260 #define USB_EP_CTRL USB_EP_DEF(0, "ep0", 0, CONTROL, EP0_FIFO_SIZE, \
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