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Searched refs:CONTROL_REG (Results 1 – 3 of 3) sorted by relevance

/drivers/char/hw_random/
Dxiphera-trng.c14 #define CONTROL_REG 0x00000000 macro
49 writel(HOST_TO_TRNG_READ, trng->mem + CONTROL_REG); in xiphera_trng_read()
50 writel(HOST_TO_TRNG_ENABLE, trng->mem + CONTROL_REG); in xiphera_trng_read()
79 writel(HOST_TO_TRNG_RESET, trng->mem + CONTROL_REG); in xiphera_trng_probe()
98 writel(HOST_TO_TRNG_RELEASE_RESET, trng->mem + CONTROL_REG); in xiphera_trng_probe()
99 writel(HOST_TO_TRNG_ENABLE, trng->mem + CONTROL_REG); in xiphera_trng_probe()
100 writel(HOST_TO_TRNG_ZEROIZE, trng->mem + CONTROL_REG); in xiphera_trng_probe()
113 writel(HOST_TO_TRNG_ACK_ZEROIZE, trng->mem + CONTROL_REG); in xiphera_trng_probe()
/drivers/net/ethernet/qlogic/
Dqla3xxx.h697 CONTROL_REG = 0, enumerator
Dqla3xxx.c1323 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, in ql_phy_reset_ex()
1393 ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, PHYAddr[qdev->mac_index]); in ql_phy_start_neg_ex()
1395 ql_mii_write_reg_ex(qdev, CONTROL_REG, in ql_phy_start_neg_ex()