Home
last modified time | relevance | path

Searched refs:CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c2976 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | in gfx_v7_0_mqd_init()
/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h3355 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000 macro
Dgfx_8_0_sh_mask.h3971 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000 macro
Dgfx_8_1_sh_mask.h4493 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h12916 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK … macro
Dgc_9_1_sh_mask.h14220 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK … macro
Dgc_9_2_1_sh_mask.h14085 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK … macro
Dgc_9_4_2_sh_mask.h4018 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK … macro
Dgc_10_1_0_sh_mask.h20208 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK … macro
Dgc_10_3_0_sh_mask.h18430 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK … macro