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Searched refs:CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK (Results 1 – 18 of 18) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_gfx_v8.c137 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in kgd_init_interrupts()
Damdgpu_amdkfd_gfx_v7.c179 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in kgd_init_interrupts()
Damdgpu_amdkfd_gfx_v10.c165 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in kgd_init_interrupts()
Damdgpu_amdkfd_gfx_v9.c186 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in kgd_gfx_v9_init_interrupts()
Damdgpu_amdkfd_gfx_v10_3.c133 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in init_interrupts_v10_3()
Dgfx_v7_0.c4735 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_gfx_eop_interrupt_state()
4740 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_gfx_eop_interrupt_state()
4786 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_compute_eop_interrupt_state()
4791 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_compute_eop_interrupt_state()
Dgfx_v6_0.c3245 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v6_0_set_gfx_eop_interrupt_state()
3250 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v6_0_set_gfx_eop_interrupt_state()
Dgfx_v8_0.c6492 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v8_0_set_compute_eop_interrupt_state()
6497 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v8_0_set_compute_eop_interrupt_state()
/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h2382 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L macro
Dgfx_7_2_sh_mask.h1185 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000 macro
Dgfx_8_0_sh_mask.h1513 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000 macro
Dgfx_8_1_sh_mask.h2037 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h11008 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro
Dgc_9_1_sh_mask.h12489 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro
Dgc_9_2_1_sh_mask.h12293 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro
Dgc_9_4_2_sh_mask.h2309 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro
Dgc_10_1_0_sh_mask.h17953 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro
Dgc_10_3_0_sh_mask.h16217 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro