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Searched refs:CRC (Results 1 – 18 of 18) sorted by relevance

/drivers/soc/samsung/
DKconfig60 bool "S3C2410 PM Suspend Memory CRC"
75 int "S3C2410 PM Suspend CRC Chunksize (KiB)"
79 Set the chunksize in Kilobytes of the CRC for checking memory
81 the CRC data block will take more memory, but will identify any
/drivers/net/ethernet/amd/
Dnmclan_cs.c1287 static void updateCRC(int *CRC, int bit) in updateCRC() argument
1301 CRC[j] = CRC[j-1]; in updateCRC()
1302 CRC[0] = 0; in updateCRC()
1305 if (bit ^ CRC[32]) in updateCRC()
1307 CRC[j] ^= poly[j]; in updateCRC()
1321 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */ in BuildLAF() local
1326 CRC[32]=0; in BuildLAF()
1330 updateCRC(CRC, (adr[byte] >> i) & 1); in BuildLAF()
1334 hashcode = (hashcode << 1) + CRC[i]; in BuildLAF()
/drivers/char/xilinx_hwicap/
Dxilinx_hwicap.c121 .CRC = 0,
146 .CRC = 0,
171 .CRC = 0,
196 .CRC = 0,
Dxilinx_hwicap.h125 u32 CRC; member
/drivers/net/wireless/marvell/libertas_tf/
Dif_usb.h76 __le32 CRC; member
/drivers/net/wireless/marvell/libertas/
Dif_usb.h86 __le32 CRC; member
/drivers/net/ethernet/intel/fm10k/
Dfm10k_mbx.c868 mbx->mbx_hdr = hdr | FM10K_MSG_HDR_FIELD_SET(crc, CRC); in fm10k_mbx_create_data_hdr()
887 mbx->mbx_hdr = hdr | FM10K_MSG_HDR_FIELD_SET(crc, CRC); in fm10k_mbx_create_disconnect_hdr()
908 mbx->mbx_hdr = hdr | FM10K_MSG_HDR_FIELD_SET(crc, CRC); in fm10k_mbx_create_fake_disconnect_hdr()
/drivers/pci/pcie/
DKconfig56 (transaction layer end-to-end CRC checking).
/drivers/crypto/
DKconfig240 tristate "CRC-32 algorithms"
246 implementations of CRC algorithms. With this option, you
247 can optimize the computation of CRC-32 (IEEE 802.3 Ethernet)
248 and CRC-32C (Castagnoli).
/drivers/w1/slaves/
DKconfig104 Full block writes are only allowed if the CRC is valid.
/drivers/scsi/aic7xxx/
Daic7xxx.reg184 field ENABLE_CRC 0x40 /* CRC for D-Phases */
356 field CRCVALERR 0x08 /* CRC doesn't match (U3 only) */
357 field CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */
358 field CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */
Daic79xx.reg2522 * CRC Control
2587 * Data Group CRC Interval.
2618 * Packetized CRC Interval
Daic79xx.seq2121 * phases that are typically caused by CRC errors in status packet
/drivers/pwm/
DKconfig154 bool "Intel Crystalcove (CRC) PWM support"
157 Generic PWM framework driver for Crystalcove (CRC) PMIC based PWM
/drivers/net/ethernet/
Dfealnx.c256 CRC = 0x08, /* crc error */ enumerator
1634 if (rx_status & CRC) in netdev_rx()
/drivers/media/dvb-frontends/drx39xyj/
Ddrxj.c1013 u16 CRC; member
11669 block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data + count)); in drx_check_firmware()
11674 block_hdr.CRC); in drx_check_firmware()
11813 block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data)); in drx_ctrl_u_code()
11818 block_hdr.size, block_hdr.flags, block_hdr.CRC); in drx_ctrl_u_code()
11826 (block_hdr.CRC != drx_u_code_compute_crc(mc_data, block_hdr.size))) in drx_ctrl_u_code()
/drivers/net/ethernet/emulex/benet/
Dbe_main.c860 BE_WRB_F_SET(wrb_params->features, CRC, 1); in be_get_wrb_params_from_skb()
871 BE_WRB_F_GET(wrb_params->features, CRC)); in wrb_fill_hdr()
/drivers/gpio/
DKconfig1597 CRC checksums to guard against electromagnetic interference,