1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_STREAM_ENCODER_DCN10_H__ 27 #define __DC_STREAM_ENCODER_DCN10_H__ 28 29 #include "stream_encoder.h" 30 31 #define DCN10STRENC_FROM_STRENC(stream_encoder)\ 32 container_of(stream_encoder, struct dcn10_stream_encoder, base) 33 34 #define SE_COMMON_DCN_REG_LIST(id) \ 35 SRI(AFMT_CNTL, DIG, id), \ 36 SRI(AFMT_GENERIC_0, DIG, id), \ 37 SRI(AFMT_GENERIC_1, DIG, id), \ 38 SRI(AFMT_GENERIC_2, DIG, id), \ 39 SRI(AFMT_GENERIC_3, DIG, id), \ 40 SRI(AFMT_GENERIC_4, DIG, id), \ 41 SRI(AFMT_GENERIC_5, DIG, id), \ 42 SRI(AFMT_GENERIC_6, DIG, id), \ 43 SRI(AFMT_GENERIC_7, DIG, id), \ 44 SRI(AFMT_GENERIC_HDR, DIG, id), \ 45 SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \ 46 SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \ 47 SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id), \ 48 SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \ 49 SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \ 50 SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \ 51 SRI(AFMT_60958_0, DIG, id), \ 52 SRI(AFMT_60958_1, DIG, id), \ 53 SRI(AFMT_60958_2, DIG, id), \ 54 SRI(DIG_FE_CNTL, DIG, id), \ 55 SRI(DIG_FIFO_STATUS, DIG, id), \ 56 SRI(HDMI_CONTROL, DIG, id), \ 57 SRI(HDMI_DB_CONTROL, DIG, id), \ 58 SRI(HDMI_GC, DIG, id), \ 59 SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \ 60 SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \ 61 SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \ 62 SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \ 63 SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \ 64 SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \ 65 SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \ 66 SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\ 67 SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\ 68 SRI(HDMI_ACR_32_0, DIG, id),\ 69 SRI(HDMI_ACR_32_1, DIG, id),\ 70 SRI(HDMI_ACR_44_0, DIG, id),\ 71 SRI(HDMI_ACR_44_1, DIG, id),\ 72 SRI(HDMI_ACR_48_0, DIG, id),\ 73 SRI(HDMI_ACR_48_1, DIG, id),\ 74 SRI(DP_DB_CNTL, DP, id), \ 75 SRI(DP_MSA_MISC, DP, id), \ 76 SRI(DP_MSA_COLORIMETRY, DP, id), \ 77 SRI(DP_MSA_TIMING_PARAM1, DP, id), \ 78 SRI(DP_MSA_TIMING_PARAM2, DP, id), \ 79 SRI(DP_MSA_TIMING_PARAM3, DP, id), \ 80 SRI(DP_MSA_TIMING_PARAM4, DP, id), \ 81 SRI(DP_MSE_RATE_CNTL, DP, id), \ 82 SRI(DP_MSE_RATE_UPDATE, DP, id), \ 83 SRI(DP_PIXEL_FORMAT, DP, id), \ 84 SRI(DP_SEC_CNTL, DP, id), \ 85 SRI(DP_SEC_CNTL1, DP, id), \ 86 SRI(DP_SEC_CNTL2, DP, id), \ 87 SRI(DP_SEC_CNTL5, DP, id), \ 88 SRI(DP_SEC_CNTL6, DP, id), \ 89 SRI(DP_STEER_FIFO, DP, id), \ 90 SRI(DP_VID_M, DP, id), \ 91 SRI(DP_VID_N, DP, id), \ 92 SRI(DP_VID_STREAM_CNTL, DP, id), \ 93 SRI(DP_VID_TIMING, DP, id), \ 94 SRI(DP_SEC_AUD_N, DP, id), \ 95 SRI(DP_SEC_TIMESTAMP, DP, id), \ 96 SRI(DIG_CLOCK_PATTERN, DIG, id) 97 98 #define SE_DCN_REG_LIST(id)\ 99 SE_COMMON_DCN_REG_LIST(id) 100 101 102 struct dcn10_stream_enc_registers { 103 uint32_t AFMT_CNTL; 104 uint32_t AFMT_AVI_INFO0; 105 uint32_t AFMT_AVI_INFO1; 106 uint32_t AFMT_AVI_INFO2; 107 uint32_t AFMT_AVI_INFO3; 108 uint32_t AFMT_GENERIC_0; 109 uint32_t AFMT_GENERIC_1; 110 uint32_t AFMT_GENERIC_2; 111 uint32_t AFMT_GENERIC_3; 112 uint32_t AFMT_GENERIC_4; 113 uint32_t AFMT_GENERIC_5; 114 uint32_t AFMT_GENERIC_6; 115 uint32_t AFMT_GENERIC_7; 116 uint32_t AFMT_GENERIC_HDR; 117 uint32_t AFMT_INFOFRAME_CONTROL0; 118 uint32_t AFMT_VBI_PACKET_CONTROL; 119 uint32_t AFMT_VBI_PACKET_CONTROL1; 120 uint32_t AFMT_AUDIO_PACKET_CONTROL; 121 uint32_t AFMT_AUDIO_PACKET_CONTROL2; 122 uint32_t AFMT_AUDIO_SRC_CONTROL; 123 uint32_t AFMT_60958_0; 124 uint32_t AFMT_60958_1; 125 uint32_t AFMT_60958_2; 126 uint32_t DIG_FE_CNTL; 127 uint32_t DIG_FE_CNTL2; 128 uint32_t DIG_FIFO_STATUS; 129 uint32_t DP_MSE_RATE_CNTL; 130 uint32_t DP_MSE_RATE_UPDATE; 131 uint32_t DP_PIXEL_FORMAT; 132 uint32_t DP_SEC_CNTL; 133 uint32_t DP_SEC_CNTL1; 134 uint32_t DP_SEC_CNTL2; 135 uint32_t DP_SEC_CNTL5; 136 uint32_t DP_SEC_CNTL6; 137 uint32_t DP_STEER_FIFO; 138 uint32_t DP_VID_M; 139 uint32_t DP_VID_N; 140 uint32_t DP_VID_STREAM_CNTL; 141 uint32_t DP_VID_TIMING; 142 uint32_t DP_SEC_AUD_N; 143 uint32_t DP_SEC_TIMESTAMP; 144 uint32_t HDMI_CONTROL; 145 uint32_t HDMI_GC; 146 uint32_t HDMI_GENERIC_PACKET_CONTROL0; 147 uint32_t HDMI_GENERIC_PACKET_CONTROL1; 148 uint32_t HDMI_GENERIC_PACKET_CONTROL2; 149 uint32_t HDMI_GENERIC_PACKET_CONTROL3; 150 uint32_t HDMI_GENERIC_PACKET_CONTROL4; 151 uint32_t HDMI_GENERIC_PACKET_CONTROL5; 152 uint32_t HDMI_INFOFRAME_CONTROL0; 153 uint32_t HDMI_INFOFRAME_CONTROL1; 154 uint32_t HDMI_VBI_PACKET_CONTROL; 155 uint32_t HDMI_AUDIO_PACKET_CONTROL; 156 uint32_t HDMI_ACR_PACKET_CONTROL; 157 uint32_t HDMI_ACR_32_0; 158 uint32_t HDMI_ACR_32_1; 159 uint32_t HDMI_ACR_44_0; 160 uint32_t HDMI_ACR_44_1; 161 uint32_t HDMI_ACR_48_0; 162 uint32_t HDMI_ACR_48_1; 163 uint32_t DP_DB_CNTL; 164 uint32_t DP_MSA_MISC; 165 uint32_t DP_MSA_VBID_MISC; 166 uint32_t DP_MSA_COLORIMETRY; 167 uint32_t DP_MSA_TIMING_PARAM1; 168 uint32_t DP_MSA_TIMING_PARAM2; 169 uint32_t DP_MSA_TIMING_PARAM3; 170 uint32_t DP_MSA_TIMING_PARAM4; 171 uint32_t HDMI_DB_CONTROL; 172 uint32_t DP_DSC_CNTL; 173 uint32_t DP_DSC_BYTES_PER_PIXEL; 174 uint32_t DME_CONTROL; 175 uint32_t DP_SEC_METADATA_TRANSMISSION; 176 uint32_t HDMI_METADATA_PACKET_CONTROL; 177 uint32_t DP_SEC_FRAMING4; 178 uint32_t DP_GSP11_CNTL; 179 uint32_t HDMI_GENERIC_PACKET_CONTROL6; 180 uint32_t HDMI_GENERIC_PACKET_CONTROL7; 181 uint32_t HDMI_GENERIC_PACKET_CONTROL8; 182 uint32_t HDMI_GENERIC_PACKET_CONTROL9; 183 uint32_t HDMI_GENERIC_PACKET_CONTROL10; 184 uint32_t DIG_CLOCK_PATTERN; 185 }; 186 187 188 #define SE_SF(reg_name, field_name, post_fix)\ 189 .field_name = reg_name ## __ ## field_name ## post_fix 190 191 #define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\ 192 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\ 193 SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\ 194 SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\ 195 SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\ 196 SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\ 197 SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\ 198 SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\ 199 SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\ 200 SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\ 201 SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\ 202 SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\ 203 SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\ 204 SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\ 205 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ 206 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ 207 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ 208 SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\ 209 SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\ 210 SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\ 211 SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\ 212 SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\ 213 SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\ 214 SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\ 215 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\ 216 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\ 217 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\ 218 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\ 219 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\ 220 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\ 221 SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND, mask_sh),\ 222 SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, mask_sh),\ 223 SE_SF(DP0_DP_SEC_CNTL4, DP_SEC_GSP4_LINE_NUM, mask_sh),\ 224 SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, mask_sh),\ 225 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\ 226 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ 227 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\ 228 SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\ 229 SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\ 230 SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\ 231 SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\ 232 SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\ 233 SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\ 234 SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\ 235 SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\ 236 SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\ 237 SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\ 238 SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\ 239 SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\ 240 SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\ 241 SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\ 242 SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\ 243 SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\ 244 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\ 245 SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\ 246 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\ 247 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ 248 SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\ 249 SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\ 250 SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\ 251 SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\ 252 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\ 253 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\ 254 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\ 255 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\ 256 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\ 257 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\ 258 SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\ 259 SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\ 260 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\ 261 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\ 262 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\ 263 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\ 264 SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\ 265 SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\ 266 SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ 267 SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ 268 SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ 269 SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ 270 SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\ 271 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_LEVEL_ERROR, mask_sh),\ 272 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_USE_OVERWRITE_LEVEL, mask_sh),\ 273 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_OVERWRITE_LEVEL, mask_sh),\ 274 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_ERROR_ACK, mask_sh),\ 275 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CAL_AVERAGE_LEVEL, mask_sh),\ 276 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MAXIMUM_LEVEL, mask_sh),\ 277 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MINIMUM_LEVEL, mask_sh),\ 278 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_READ_CLOCK_SRC, mask_sh),\ 279 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CALIBRATED, mask_sh),\ 280 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECAL_AVERAGE, mask_sh),\ 281 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECOMP_MINMAX, mask_sh),\ 282 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\ 283 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\ 284 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\ 285 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\ 286 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\ 287 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\ 288 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\ 289 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\ 290 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING, mask_sh),\ 291 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\ 292 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\ 293 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\ 294 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\ 295 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\ 296 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\ 297 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\ 298 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\ 299 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_IMMEDIATE_UPDATE, mask_sh),\ 300 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_IMMEDIATE_UPDATE, mask_sh),\ 301 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_IMMEDIATE_UPDATE, mask_sh),\ 302 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_IMMEDIATE_UPDATE, mask_sh),\ 303 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE, mask_sh),\ 304 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_IMMEDIATE_UPDATE, mask_sh),\ 305 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_IMMEDIATE_UPDATE, mask_sh),\ 306 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_IMMEDIATE_UPDATE, mask_sh),\ 307 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\ 308 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\ 309 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\ 310 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\ 311 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\ 312 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\ 313 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\ 314 SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_PPS, mask_sh),\ 315 SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\ 316 SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\ 317 SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\ 318 SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\ 319 SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\ 320 SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\ 321 SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\ 322 SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\ 323 SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\ 324 SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\ 325 SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\ 326 SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\ 327 SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\ 328 SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\ 329 SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\ 330 SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\ 331 SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh),\ 332 SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh) 333 334 #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ 335 SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) 336 337 #define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\ 338 SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\ 339 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\ 340 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\ 341 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\ 342 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\ 343 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\ 344 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh) 345 346 347 #define SE_REG_FIELD_LIST_DCN1_0(type) \ 348 type AFMT_GENERIC_INDEX;\ 349 type AFMT_GENERIC_HB0;\ 350 type AFMT_GENERIC_HB1;\ 351 type AFMT_GENERIC_HB2;\ 352 type AFMT_GENERIC_HB3;\ 353 type AFMT_GENERIC_LOCK_STATUS;\ 354 type AFMT_GENERIC_CONFLICT;\ 355 type AFMT_GENERIC_CONFLICT_CLR;\ 356 type AFMT_GENERIC0_FRAME_UPDATE_PENDING;\ 357 type AFMT_GENERIC1_FRAME_UPDATE_PENDING;\ 358 type AFMT_GENERIC2_FRAME_UPDATE_PENDING;\ 359 type AFMT_GENERIC3_FRAME_UPDATE_PENDING;\ 360 type AFMT_GENERIC4_FRAME_UPDATE_PENDING;\ 361 type AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING;\ 362 type AFMT_GENERIC5_FRAME_UPDATE_PENDING;\ 363 type AFMT_GENERIC6_FRAME_UPDATE_PENDING;\ 364 type AFMT_GENERIC7_FRAME_UPDATE_PENDING;\ 365 type AFMT_GENERIC0_FRAME_UPDATE;\ 366 type AFMT_GENERIC1_FRAME_UPDATE;\ 367 type AFMT_GENERIC2_FRAME_UPDATE;\ 368 type AFMT_GENERIC3_FRAME_UPDATE;\ 369 type AFMT_GENERIC4_FRAME_UPDATE;\ 370 type AFMT_GENERIC0_IMMEDIATE_UPDATE;\ 371 type AFMT_GENERIC1_IMMEDIATE_UPDATE;\ 372 type AFMT_GENERIC2_IMMEDIATE_UPDATE;\ 373 type AFMT_GENERIC3_IMMEDIATE_UPDATE;\ 374 type AFMT_GENERIC4_IMMEDIATE_UPDATE;\ 375 type AFMT_GENERIC5_IMMEDIATE_UPDATE;\ 376 type AFMT_GENERIC6_IMMEDIATE_UPDATE;\ 377 type AFMT_GENERIC7_IMMEDIATE_UPDATE;\ 378 type AFMT_GENERIC5_FRAME_UPDATE;\ 379 type AFMT_GENERIC6_FRAME_UPDATE;\ 380 type AFMT_GENERIC7_FRAME_UPDATE;\ 381 type HDMI_GENERIC0_CONT;\ 382 type HDMI_GENERIC0_SEND;\ 383 type HDMI_GENERIC0_LINE;\ 384 type HDMI_GENERIC1_CONT;\ 385 type HDMI_GENERIC1_SEND;\ 386 type HDMI_GENERIC1_LINE;\ 387 type HDMI_GENERIC2_CONT;\ 388 type HDMI_GENERIC2_SEND;\ 389 type HDMI_GENERIC2_LINE;\ 390 type HDMI_GENERIC3_CONT;\ 391 type HDMI_GENERIC3_SEND;\ 392 type HDMI_GENERIC3_LINE;\ 393 type HDMI_GENERIC4_CONT;\ 394 type HDMI_GENERIC4_SEND;\ 395 type HDMI_GENERIC4_LINE;\ 396 type HDMI_GENERIC5_CONT;\ 397 type HDMI_GENERIC5_SEND;\ 398 type HDMI_GENERIC5_LINE;\ 399 type HDMI_GENERIC6_CONT;\ 400 type HDMI_GENERIC6_SEND;\ 401 type HDMI_GENERIC6_LINE;\ 402 type HDMI_GENERIC7_CONT;\ 403 type HDMI_GENERIC7_SEND;\ 404 type HDMI_GENERIC7_LINE;\ 405 type DP_PIXEL_ENCODING;\ 406 type DP_COMPONENT_DEPTH;\ 407 type HDMI_PACKET_GEN_VERSION;\ 408 type HDMI_KEEPOUT_MODE;\ 409 type HDMI_DEEP_COLOR_ENABLE;\ 410 type HDMI_CLOCK_CHANNEL_RATE;\ 411 type HDMI_DEEP_COLOR_DEPTH;\ 412 type HDMI_GC_CONT;\ 413 type HDMI_GC_SEND;\ 414 type HDMI_NULL_SEND;\ 415 type HDMI_DATA_SCRAMBLE_EN;\ 416 type HDMI_NO_EXTRA_NULL_PACKET_FILLED;\ 417 type HDMI_AUDIO_INFO_SEND;\ 418 type AFMT_AUDIO_INFO_UPDATE;\ 419 type HDMI_AUDIO_INFO_LINE;\ 420 type HDMI_GC_AVMUTE;\ 421 type DP_MSE_RATE_X;\ 422 type DP_MSE_RATE_Y;\ 423 type DP_MSE_RATE_UPDATE_PENDING;\ 424 type DP_SEC_GSP0_ENABLE;\ 425 type DP_SEC_STREAM_ENABLE;\ 426 type DP_SEC_GSP1_ENABLE;\ 427 type DP_SEC_GSP2_ENABLE;\ 428 type DP_SEC_GSP3_ENABLE;\ 429 type DP_SEC_GSP4_ENABLE;\ 430 type DP_SEC_GSP5_ENABLE;\ 431 type DP_SEC_GSP5_LINE_NUM;\ 432 type DP_SEC_GSP5_LINE_REFERENCE;\ 433 type DP_SEC_GSP6_ENABLE;\ 434 type DP_SEC_GSP7_ENABLE;\ 435 type DP_SEC_GSP7_PPS;\ 436 type DP_SEC_GSP7_SEND;\ 437 type DP_SEC_GSP4_SEND;\ 438 type DP_SEC_GSP4_SEND_PENDING;\ 439 type DP_SEC_GSP4_LINE_NUM;\ 440 type DP_SEC_GSP4_SEND_ANY_LINE;\ 441 type DP_SEC_MPG_ENABLE;\ 442 type DP_VID_STREAM_DIS_DEFER;\ 443 type DP_VID_STREAM_ENABLE;\ 444 type DP_VID_STREAM_STATUS;\ 445 type DP_STEER_FIFO_RESET;\ 446 type DP_VID_M_N_GEN_EN;\ 447 type DP_VID_N;\ 448 type DP_VID_M;\ 449 type DIG_START;\ 450 type AFMT_AUDIO_SRC_SELECT;\ 451 type AFMT_AUDIO_CHANNEL_ENABLE;\ 452 type HDMI_AUDIO_PACKETS_PER_LINE;\ 453 type HDMI_AUDIO_DELAY_EN;\ 454 type AFMT_60958_CS_UPDATE;\ 455 type AFMT_AUDIO_LAYOUT_OVRD;\ 456 type AFMT_60958_OSF_OVRD;\ 457 type HDMI_ACR_AUTO_SEND;\ 458 type HDMI_ACR_SOURCE;\ 459 type HDMI_ACR_AUDIO_PRIORITY;\ 460 type HDMI_ACR_CTS_32;\ 461 type HDMI_ACR_N_32;\ 462 type HDMI_ACR_CTS_44;\ 463 type HDMI_ACR_N_44;\ 464 type HDMI_ACR_CTS_48;\ 465 type HDMI_ACR_N_48;\ 466 type AFMT_60958_CS_CHANNEL_NUMBER_L;\ 467 type AFMT_60958_CS_CLOCK_ACCURACY;\ 468 type AFMT_60958_CS_CHANNEL_NUMBER_R;\ 469 type AFMT_60958_CS_CHANNEL_NUMBER_2;\ 470 type AFMT_60958_CS_CHANNEL_NUMBER_3;\ 471 type AFMT_60958_CS_CHANNEL_NUMBER_4;\ 472 type AFMT_60958_CS_CHANNEL_NUMBER_5;\ 473 type AFMT_60958_CS_CHANNEL_NUMBER_6;\ 474 type AFMT_60958_CS_CHANNEL_NUMBER_7;\ 475 type DP_SEC_AUD_N;\ 476 type DP_SEC_TIMESTAMP_MODE;\ 477 type DP_SEC_ASP_ENABLE;\ 478 type DP_SEC_ATP_ENABLE;\ 479 type DP_SEC_AIP_ENABLE;\ 480 type DP_SEC_ACM_ENABLE;\ 481 type DP_SEC_GSP7_LINE_NUM;\ 482 type AFMT_AUDIO_SAMPLE_SEND;\ 483 type AFMT_AUDIO_CLOCK_EN;\ 484 type TMDS_PIXEL_ENCODING;\ 485 type TMDS_COLOR_FORMAT;\ 486 type DIG_STEREOSYNC_SELECT;\ 487 type DIG_STEREOSYNC_GATE_EN;\ 488 type DP_DB_DISABLE;\ 489 type DP_MSA_MISC0;\ 490 type DP_MSA_HTOTAL;\ 491 type DP_MSA_VTOTAL;\ 492 type DP_MSA_HSTART;\ 493 type DP_MSA_VSTART;\ 494 type DP_MSA_HSYNCWIDTH;\ 495 type DP_MSA_HSYNCPOLARITY;\ 496 type DP_MSA_VSYNCWIDTH;\ 497 type DP_MSA_VSYNCPOLARITY;\ 498 type DP_MSA_HWIDTH;\ 499 type DP_MSA_VHEIGHT;\ 500 type HDMI_DB_DISABLE;\ 501 type DP_VID_N_MUL;\ 502 type DP_VID_M_DOUBLE_VALUE_EN;\ 503 type DIG_SOURCE_SELECT;\ 504 type DIG_FIFO_LEVEL_ERROR;\ 505 type DIG_FIFO_USE_OVERWRITE_LEVEL;\ 506 type DIG_FIFO_OVERWRITE_LEVEL;\ 507 type DIG_FIFO_ERROR_ACK;\ 508 type DIG_FIFO_CAL_AVERAGE_LEVEL;\ 509 type DIG_FIFO_MAXIMUM_LEVEL;\ 510 type DIG_FIFO_MINIMUM_LEVEL;\ 511 type DIG_FIFO_READ_CLOCK_SRC;\ 512 type DIG_FIFO_CALIBRATED;\ 513 type DIG_FIFO_FORCE_RECAL_AVERAGE;\ 514 type DIG_FIFO_FORCE_RECOMP_MINMAX;\ 515 type DIG_CLOCK_PATTERN 516 517 #define SE_REG_FIELD_LIST_DCN2_0(type) \ 518 type DP_DSC_MODE;\ 519 type DP_DSC_SLICE_WIDTH;\ 520 type DP_DSC_BYTES_PER_PIXEL;\ 521 type DP_VBID6_LINE_REFERENCE;\ 522 type DP_VBID6_LINE_NUM;\ 523 type METADATA_ENGINE_EN;\ 524 type METADATA_HUBP_REQUESTOR_ID;\ 525 type METADATA_STREAM_TYPE;\ 526 type DP_SEC_METADATA_PACKET_ENABLE;\ 527 type DP_SEC_METADATA_PACKET_LINE_REFERENCE;\ 528 type DP_SEC_METADATA_PACKET_LINE;\ 529 type HDMI_METADATA_PACKET_ENABLE;\ 530 type HDMI_METADATA_PACKET_LINE_REFERENCE;\ 531 type HDMI_METADATA_PACKET_LINE;\ 532 type DOLBY_VISION_EN;\ 533 type DP_PIXEL_COMBINE;\ 534 type DP_SST_SDP_SPLITTING 535 536 #define SE_REG_FIELD_LIST_DCN3_0(type) \ 537 type HDMI_GENERIC8_CONT;\ 538 type HDMI_GENERIC8_SEND;\ 539 type HDMI_GENERIC8_LINE;\ 540 type HDMI_GENERIC9_CONT;\ 541 type HDMI_GENERIC9_SEND;\ 542 type HDMI_GENERIC9_LINE;\ 543 type HDMI_GENERIC10_CONT;\ 544 type HDMI_GENERIC10_SEND;\ 545 type HDMI_GENERIC10_LINE;\ 546 type HDMI_GENERIC11_CONT;\ 547 type HDMI_GENERIC11_SEND;\ 548 type HDMI_GENERIC11_LINE;\ 549 type HDMI_GENERIC12_CONT;\ 550 type HDMI_GENERIC12_SEND;\ 551 type HDMI_GENERIC12_LINE;\ 552 type HDMI_GENERIC13_CONT;\ 553 type HDMI_GENERIC13_SEND;\ 554 type HDMI_GENERIC13_LINE;\ 555 type HDMI_GENERIC14_CONT;\ 556 type HDMI_GENERIC14_SEND;\ 557 type HDMI_GENERIC14_LINE;\ 558 type DP_SEC_GSP11_PPS;\ 559 type DP_SEC_GSP11_ENABLE;\ 560 type DP_SEC_GSP11_LINE_NUM 561 562 struct dcn10_stream_encoder_shift { 563 SE_REG_FIELD_LIST_DCN1_0(uint8_t); 564 SE_REG_FIELD_LIST_DCN2_0(uint8_t); 565 SE_REG_FIELD_LIST_DCN3_0(uint8_t); 566 }; 567 568 struct dcn10_stream_encoder_mask { 569 SE_REG_FIELD_LIST_DCN1_0(uint32_t); 570 SE_REG_FIELD_LIST_DCN2_0(uint32_t); 571 SE_REG_FIELD_LIST_DCN3_0(uint32_t); 572 }; 573 574 struct dcn10_stream_encoder { 575 struct stream_encoder base; 576 const struct dcn10_stream_enc_registers *regs; 577 const struct dcn10_stream_encoder_shift *se_shift; 578 const struct dcn10_stream_encoder_mask *se_mask; 579 }; 580 581 void dcn10_stream_encoder_construct( 582 struct dcn10_stream_encoder *enc1, 583 struct dc_context *ctx, 584 struct dc_bios *bp, 585 enum engine_id eng_id, 586 const struct dcn10_stream_enc_registers *regs, 587 const struct dcn10_stream_encoder_shift *se_shift, 588 const struct dcn10_stream_encoder_mask *se_mask); 589 590 void enc1_update_generic_info_packet( 591 struct dcn10_stream_encoder *enc1, 592 uint32_t packet_index, 593 const struct dc_info_packet *info_packet); 594 595 void enc1_stream_encoder_dp_set_stream_attribute( 596 struct stream_encoder *enc, 597 struct dc_crtc_timing *crtc_timing, 598 enum dc_color_space output_color_space, 599 bool use_vsc_sdp_for_colorimetry, 600 uint32_t enable_sdp_splitting); 601 602 void enc1_stream_encoder_hdmi_set_stream_attribute( 603 struct stream_encoder *enc, 604 struct dc_crtc_timing *crtc_timing, 605 int actual_pix_clk_khz, 606 bool enable_audio); 607 608 void enc1_stream_encoder_dvi_set_stream_attribute( 609 struct stream_encoder *enc, 610 struct dc_crtc_timing *crtc_timing, 611 bool is_dual_link); 612 613 void enc1_stream_encoder_set_throttled_vcp_size( 614 struct stream_encoder *enc, 615 struct fixed31_32 avg_time_slots_per_mtp); 616 617 void enc1_stream_encoder_update_dp_info_packets( 618 struct stream_encoder *enc, 619 const struct encoder_info_frame *info_frame); 620 621 void enc1_stream_encoder_send_immediate_sdp_message( 622 struct stream_encoder *enc, 623 const uint8_t *custom_sdp_message, 624 unsigned int sdp_message_size); 625 626 void enc1_stream_encoder_stop_dp_info_packets( 627 struct stream_encoder *enc); 628 629 void enc1_stream_encoder_dp_blank( 630 struct stream_encoder *enc); 631 632 void enc1_stream_encoder_dp_unblank( 633 struct stream_encoder *enc, 634 const struct encoder_unblank_param *param); 635 636 void enc1_setup_stereo_sync( 637 struct stream_encoder *enc, 638 int tg_inst, bool enable); 639 640 void enc1_stream_encoder_set_avmute( 641 struct stream_encoder *enc, 642 bool enable); 643 644 void enc1_se_audio_mute_control( 645 struct stream_encoder *enc, 646 bool mute); 647 648 void enc1_se_dp_audio_setup( 649 struct stream_encoder *enc, 650 unsigned int az_inst, 651 struct audio_info *info); 652 653 void enc1_se_dp_audio_enable( 654 struct stream_encoder *enc); 655 656 void enc1_se_dp_audio_disable( 657 struct stream_encoder *enc); 658 659 void enc1_se_hdmi_audio_setup( 660 struct stream_encoder *enc, 661 unsigned int az_inst, 662 struct audio_info *info, 663 struct audio_crtc_info *audio_crtc_info); 664 665 void enc1_se_hdmi_audio_disable( 666 struct stream_encoder *enc); 667 668 void enc1_dig_connect_to_otg( 669 struct stream_encoder *enc, 670 int tg_inst); 671 672 unsigned int enc1_dig_source_otg( 673 struct stream_encoder *enc); 674 675 void enc1_stream_encoder_set_stream_attribute_helper( 676 struct dcn10_stream_encoder *enc1, 677 struct dc_crtc_timing *crtc_timing); 678 679 void enc1_se_enable_audio_clock( 680 struct stream_encoder *enc, 681 bool enable); 682 683 void enc1_se_enable_dp_audio( 684 struct stream_encoder *enc); 685 686 void get_audio_clock_info( 687 enum dc_color_depth color_depth, 688 uint32_t crtc_pixel_clock_100Hz, 689 uint32_t actual_pixel_clock_100Hz, 690 struct audio_clock_info *audio_clock_info); 691 692 void enc1_reset_hdmi_stream_attribute( 693 struct stream_encoder *enc); 694 695 bool enc1_stream_encoder_dp_get_pixel_format( 696 struct stream_encoder *enc, 697 enum dc_pixel_encoding *encoding, 698 enum dc_color_depth *depth); 699 700 #endif /* __DC_STREAM_ENCODER_DCN10_H__ */ 701