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Searched refs:DPLL (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_dpll.c1380 i915_reg_t reg = DPLL(crtc->pipe); in i9xx_enable_pll()
1457 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1458 intel_de_posting_read(dev_priv, DPLL(pipe)); in _vlv_enable_pll()
1461 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _vlv_enable_pll()
1508 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll()
1511 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _chv_enable_pll()
1547 (intel_de_read(dev_priv, DPLL(PIPE_B)) & in chv_enable_pll()
1567 intel_de_write(dev_priv, DPLL(pipe), in vlv_prepare_pll()
1668 intel_de_write(dev_priv, DPLL(pipe), in chv_prepare_pll()
1811 intel_de_write(dev_priv, DPLL(pipe), val); in vlv_disable_pll()
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Dintel_dvo.c491 dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); in intel_dvo_init()
492 intel_de_write(dev_priv, DPLL(pipe), in intel_dvo_init()
500 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); in intel_dvo_init()
Dintel_display.c299 val = intel_de_read(dev_priv, DPLL(pipe)); in assert_pll()
588 dpll_reg = DPLL(0); in vlv_wait_port_ready()
592 dpll_reg = DPLL(0); in vlv_wait_port_ready()
4981 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); in i9xx_get_pipe_config()
4992 DPLL(crtc->pipe)); in i9xx_get_pipe_config()
12465 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i830_enable_pipe()
12466 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe()
12469 intel_de_posting_read(dev_priv, DPLL(pipe)); in i830_enable_pipe()
12477 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe()
12481 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe()
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Dintel_display_power.c1418 u32 val = intel_de_read(dev_priv, DPLL(pipe)); in vlv_display_power_well_init()
1424 intel_de_write(dev_priv, DPLL(pipe), val); in vlv_display_power_well_init()
1581 (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
5903 u32 status = intel_de_read(dev_priv, DPLL(PIPE_A)); in chv_phy_control_init()
Dintel_pps.c81 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
Dreg.h256 #define DPLL 0x034A macro
/drivers/gpu/drm/i915/
Di915_reg.h3479 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) macro