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Searched refs:DPLL_VCO_ENABLE (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/gma500/
Doaktrail_crtc.c243 if ((temp & DPLL_VCO_ENABLE) == 0) { in oaktrail_crtc_dpms()
249 temp | DPLL_VCO_ENABLE, i); in oaktrail_crtc_dpms()
254 temp | DPLL_VCO_ENABLE, i); in oaktrail_crtc_dpms()
315 if ((temp & DPLL_VCO_ENABLE) != 0) { in oaktrail_crtc_dpms()
317 temp & ~DPLL_VCO_ENABLE, i); in oaktrail_crtc_dpms()
526 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set()
550 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set()
552 if (dpll & DPLL_VCO_ENABLE) { in oaktrail_crtc_mode_set()
555 REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); in oaktrail_crtc_mode_set()
Dgma_display.c216 if ((temp & DPLL_VCO_ENABLE) == 0) { in gma_crtc_dpms()
221 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
304 if ((temp & DPLL_VCO_ENABLE) != 0) { in gma_crtc_dpms()
305 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
633 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { in gma_crtc_restore()
635 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); in gma_crtc_restore()
Dpsb_intel_display.c203 dpll |= DPLL_VCO_ENABLE; in psb_intel_crtc_mode_set()
212 if (dpll & DPLL_VCO_ENABLE) { in psb_intel_crtc_mode_set()
214 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set()
Dcdv_intel_display.c752 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
762 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
Dpsb_intel_reg.h229 #define DPLL_VCO_ENABLE (1 << 31) macro
/drivers/gpu/drm/i915/display/
Dintel_dpll.c861 dpll |= DPLL_VCO_ENABLE; in i9xx_compute_dpll()
917 dpll |= DPLL_VCO_ENABLE; in i8xx_compute_dpll()
1046 dpll |= DPLL_VCO_ENABLE; in ilk_compute_dpll()
1122 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
1139 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
1476 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in vlv_enable_pll()
1526 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in chv_enable_pll()
1568 pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); in vlv_prepare_pll()
1571 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_prepare_pll()
1669 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_prepare_pll()
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Dintel_pps.c81 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
Dintel_display.c300 cur_state = !!(val & DPLL_VCO_ENABLE); in assert_pll()
4817 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
4845 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
5069 if (!(temp & DPLL_VCO_ENABLE)) in ilk_init_pch_refclk()
12447 DPLL_VCO_ENABLE; in i830_enable_pipe()
Dintel_dpll_mgr.c451 return val & DPLL_VCO_ENABLE; in ibx_pch_dpll_get_hw_state()
Dintel_display_power.c1581 (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
/drivers/video/fbdev/intelfb/
Dintelfbhw.h149 #define DPLL_VCO_ENABLE (1 << 31) macro
Dintelfbhw.c1108 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE); in intelfbhw_mode_to_hw()
1399 tmp &= ~DPLL_VCO_ENABLE; in intelfbhw_program_mode()
Dintelfbdrv.c1339 OUTREG(DPLL_A, INREG(DPLL_A) & ~DPLL_VCO_ENABLE); in intelfb_set_par()
/drivers/gpu/drm/i915/
Di915_reg.h3492 #define DPLL_VCO_ENABLE (1 << 31) macro