Home
last modified time | relevance | path

Searched refs:DWB_OGAM_RAMA_END_CNTL1_B (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dwb.h92 SR(DWB_OGAM_RAMA_END_CNTL1_B),\
250 SF_DWB2(DWB_OGAM_RAMA_END_CNTL1_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
797 uint32_t DWB_OGAM_RAMA_END_CNTL1_B; member
Ddcn30_dwb_cm.c98 gam_regs.start_end_cntl1_b = REG(DWB_OGAM_RAMA_END_CNTL1_B); in dwb3_program_ogam_luta_settings()