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Searched refs:EMC_FBIO_CFG5 (Results 1 – 6 of 6) sorted by relevance

/drivers/memory/tegra/
Dtegra210-emc-core.c162 EMC_FBIO_CFG5,
1314 EMC_FBIO_CFG5, (100000 / clk) + 10); in tegra210_emc_dvfs_power_ramp_up()
1320 EMC_FBIO_CFG5, (100000 / clk) + 10); in tegra210_emc_dvfs_power_ramp_up()
1326 EMC_FBIO_CFG5, 12); in tegra210_emc_dvfs_power_ramp_up()
1358 EMC_FBIO_CFG5, 12); in tegra210_emc_dvfs_power_ramp_down()
1786 value = emc_readl(emc, EMC_FBIO_CFG5); in tegra210_emc_detect()
Dtegra20-emc.c71 #define EMC_FBIO_CFG5 0x104 macro
147 EMC_FBIO_CFG5,
492 emc_fbio = readl_relaxed(emc->regs + EMC_FBIO_CFG5); in emc_setup_hw()
Dtegra30-emc.c86 #define EMC_FBIO_CFG5 0x104 macro
265 [39] = EMC_FBIO_CFG5,
556 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5); in emc_prepare_timing_change()
1044 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5); in emc_setup_hw()
Dtegra124-emc.c31 #define EMC_FBIO_CFG5 0x104 macro
354 EMC_FBIO_CFG5,
901 emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5); in emc_init()
Dtegra210-emc.h104 #define EMC_FBIO_CFG5 0x104 macro
Dtegra210-emc-cc-r21021.c630 value = emc_readl(emc, EMC_FBIO_CFG5) & EMC_FBIO_CFG5_DRAM_TYPE_MASK; in tegra210_emc_r21021_set_clock()