| /drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v1_0.c | 159 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
352 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v1_0_gart_disable()
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| D | gfxhub_v2_0.c | 193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs()
372 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v2_0_gart_disable()
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| D | gfxhub_v2_1.c | 194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_1_init_tlb_regs()
393 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v2_1_gart_disable()
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| D | mmhub_v2_0.c | 266 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_0_init_tlb_regs()
457 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v2_0_gart_disable()
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| D | mmhub_v2_3.c | 191 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_3_init_tlb_regs()
384 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v2_3_gart_disable()
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| D | mmhub_v1_0.c | 142 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
352 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v1_0_gart_disable()
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| D | gmc_v7_0.c | 632 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gmc_v7_0_gart_enable()
753 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gmc_v7_0_gart_disable()
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| D | mmhub_v1_7.c | 162 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_7_init_tlb_regs()
362 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v1_7_gart_disable()
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| D | gmc_v8_0.c | 855 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gmc_v8_0_gart_enable()
993 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gmc_v8_0_gart_disable()
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| D | mmhub_v9_4.c | 185 ENABLE_L1_TLB, 1); in mmhub_v9_4_init_tlb_regs()
416 ENABLE_L1_TLB, 0); in mmhub_v9_4_gart_disable()
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| D | sid.h | 476 #define ENABLE_L1_TLB (1 << 0) macro
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hubp.h | 406 HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
606 type ENABLE_L1_TLB;\
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| D | dcn10_hubp.c | 821 ENABLE_L1_TLB, 1, in hubp1_set_vm_context0_settings()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hubp.c | 68 ENABLE_L1_TLB, 1, in hubp3_set_vm_system_aperture_settings()
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| /drivers/gpu/drm/radeon/ |
| D | rv770.c | 923 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
1000 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in rv770_agp_enable()
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| D | rv770d.h | 465 #define ENABLE_L1_TLB (1 << 0) macro
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| D | nid.h | 179 #define ENABLE_L1_TLB (1 << 0) macro
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| D | sid.h | 475 #define ENABLE_L1_TLB (1 << 0) macro
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| D | cikd.h | 600 #define ENABLE_L1_TLB (1 << 0) macro
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| D | evergreend.h | 955 #define ENABLE_L1_TLB (1 << 0) macro
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| D | ni.c | 1275 ENABLE_L1_TLB | in cayman_pcie_gart_enable()
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| D | r600d.h | 332 #define ENABLE_L1_TLB (1 << 0) macro
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_hubp.c | 247 ENABLE_L1_TLB, 1, in hubp21_set_vm_system_aperture_settings()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_hwseq.h | 1012 type ENABLE_L1_TLB;\
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hubp.c | 75 ENABLE_L1_TLB, 1, in hubp2_set_vm_system_aperture_settings()
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