| /drivers/visorbus/ |
| D | visorchannel.c | 169 #define SIG_WRITE_FIELD(channel, queue, sig_hdr, FIELD) \ argument
172 offsetof(struct signal_queue_header, FIELD), \
173 &((sig_hdr)->FIELD), \
174 sizeof((sig_hdr)->FIELD))
|
| /drivers/gpu/drm/msm/disp/mdp5/ |
| D | mdp5_plane.c | 734 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT), in mdp5_write_pixel_ext()
735 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT), in mdp5_write_pixel_ext()
736 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF), in mdp5_write_pixel_ext()
737 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF), in mdp5_write_pixel_ext()
738 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT)); in mdp5_write_pixel_ext()
741 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT), in mdp5_write_pixel_ext()
742 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT), in mdp5_write_pixel_ext()
743 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF), in mdp5_write_pixel_ext()
744 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF), in mdp5_write_pixel_ext()
745 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM)); in mdp5_write_pixel_ext()
|
| D | mdp5_kms.c | 552 *major = FIELD(version, MDP5_HW_VERSION_MAJOR); in read_mdp_hw_revision()
553 *minor = FIELD(version, MDP5_HW_VERSION_MINOR); in read_mdp_hw_revision()
|
| /drivers/scsi/aic7xxx/aicasm/ |
| D | aicasm_symbol.c | 102 case FIELD: in symbol_delete()
242 case FIELD: in symlist_add()
502 case FIELD: in symtable_dump()
629 case FIELD: in symtable_dump()
|
| D | aicasm_symbol.h | 54 FIELD, enumerator
|
| D | aicasm_gram.y | 476 process_field(FIELD, $2, $3.value);
484 process_field(FIELD, $2, $3.value);
707 case FIELD:
1510 case FIELD: in initialize_symbol()
1895 || node->symbol->type == FIELD in type_check()
|
| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu.h | 1177 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) argument
1178 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) argument
|
| /drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy_28nm.c | 260 sdm_byp_div = FIELD( in dsi_pll_28nm_clk_recalc_rate()
266 sdm_dc_off = FIELD( in dsi_pll_28nm_clk_recalc_rate()
270 sdm2 = FIELD(dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2), in dsi_pll_28nm_clk_recalc_rate()
272 sdm3 = FIELD(dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3), in dsi_pll_28nm_clk_recalc_rate()
|
| /drivers/gpu/drm/mediatek/ |
| D | mtk_dpi_regs.h | 136 #define FIELD BIT(20) macro
|
| /drivers/gpu/drm/msm/disp/mdp4/ |
| D | mdp4_kms.c | 394 *major = FIELD(version, MDP4_VERSION_MAJOR); in read_mdp_hw_revision()
395 *minor = FIELD(version, MDP4_VERSION_MINOR); in read_mdp_hw_revision()
|
| /drivers/gpu/drm/msm/hdmi/ |
| D | hdmi_i2c.c | 201 p->buf[j] = FIELD(ddc_data, HDMI_DDC_DATA_DATA); in msm_hdmi_i2c_xfer()
|
| /drivers/gpu/drm/radeon/ |
| D | radeon.h | 2551 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) argument
2552 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) argument
|
| /drivers/gpu/drm/msm/ |
| D | msm_drv.h | 498 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) macro
|
| /drivers/net/ethernet/mellanox/mlxsw/ |
| D | spectrum_ptp.c | 1100 #define MLXSW_SP_PTP_PORT_STAT(NAME, FIELD) \ argument
1104 FIELD), \
|
| /drivers/gpu/drm/msm/dsi/ |
| D | dsi_host.c | 55 ver = FIELD(ver, DSI_VERSION_MAJOR); in dsi_get_version()
71 ver = FIELD(ver, DSI_VERSION_MAJOR); in dsi_get_version()
|