Searched refs:GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR (Results 1 – 2 of 2) sorted by relevance
| /drivers/net/ethernet/marvell/mvpp2/ | ||
| D | mvpp2.h | 671 #define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31) macro |
| D | mvpp2_main.c | 1670 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; in mvpp22_gop_init() |