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Searched refs:HSW_CACHEABILITY_CONTROL (Results 1 – 1 of 1) sorted by relevance

/drivers/gpu/drm/i915/gt/
Dintel_gtt.h96 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ macro
98 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
99 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
100 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
101 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
102 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
103 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)