1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 */
5
6 #ifndef ATH11K_DP_H
7 #define ATH11K_DP_H
8
9 #include "hal_rx.h"
10
11 #define MAX_RXDMA_PER_PDEV 2
12
13 struct ath11k_base;
14 struct ath11k_peer;
15 struct ath11k_dp;
16 struct ath11k_vif;
17 struct hal_tcl_status_ring;
18 struct ath11k_ext_irq_grp;
19
20 struct dp_rx_tid {
21 u8 tid;
22 u32 *vaddr;
23 dma_addr_t paddr;
24 u32 size;
25 u32 ba_win_sz;
26 bool active;
27
28 /* Info related to rx fragments */
29 u32 cur_sn;
30 u16 last_frag_no;
31 u16 rx_frag_bitmap;
32
33 struct sk_buff_head rx_frags;
34 struct hal_reo_dest_ring *dst_ring_desc;
35
36 /* Timer info related to fragments */
37 struct timer_list frag_timer;
38 struct ath11k_base *ab;
39 };
40
41 #define DP_REO_DESC_FREE_THRESHOLD 64
42 #define DP_REO_DESC_FREE_TIMEOUT_MS 1000
43 #define DP_MON_PURGE_TIMEOUT_MS 100
44 #define DP_MON_SERVICE_BUDGET 128
45
46 struct dp_reo_cache_flush_elem {
47 struct list_head list;
48 struct dp_rx_tid data;
49 unsigned long ts;
50 };
51
52 struct dp_reo_cmd {
53 struct list_head list;
54 struct dp_rx_tid data;
55 int cmd_num;
56 void (*handler)(struct ath11k_dp *, void *,
57 enum hal_reo_cmd_status status);
58 };
59
60 struct dp_srng {
61 u32 *vaddr_unaligned;
62 u32 *vaddr;
63 dma_addr_t paddr_unaligned;
64 dma_addr_t paddr;
65 int size;
66 u32 ring_id;
67 };
68
69 struct dp_rxdma_ring {
70 struct dp_srng refill_buf_ring;
71 struct idr bufs_idr;
72 /* Protects bufs_idr */
73 spinlock_t idr_lock;
74 int bufs_max;
75 };
76
77 #define ATH11K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE)
78
79 struct dp_tx_ring {
80 u8 tcl_data_ring_id;
81 struct dp_srng tcl_data_ring;
82 struct dp_srng tcl_comp_ring;
83 struct idr txbuf_idr;
84 /* Protects txbuf_idr and num_pending */
85 spinlock_t tx_idr_lock;
86 struct hal_wbm_release_ring *tx_status;
87 int tx_status_head;
88 int tx_status_tail;
89 };
90
91 struct ath11k_pdev_mon_stats {
92 u32 status_ppdu_state;
93 u32 status_ppdu_start;
94 u32 status_ppdu_end;
95 u32 status_ppdu_compl;
96 u32 status_ppdu_start_mis;
97 u32 status_ppdu_end_mis;
98 u32 status_ppdu_done;
99 u32 dest_ppdu_done;
100 u32 dest_mpdu_done;
101 u32 dest_mpdu_drop;
102 u32 dup_mon_linkdesc_cnt;
103 u32 dup_mon_buf_cnt;
104 };
105
106 struct dp_link_desc_bank {
107 void *vaddr_unaligned;
108 void *vaddr;
109 dma_addr_t paddr_unaligned;
110 dma_addr_t paddr;
111 u32 size;
112 };
113
114 /* Size to enforce scatter idle list mode */
115 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000
116 #define DP_LINK_DESC_BANKS_MAX 8
117
118 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff
119 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000
120 #define DP_RX_DESC_COOKIE_MAX \
121 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX)
122 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000
123
124 enum ath11k_dp_ppdu_state {
125 DP_PPDU_STATUS_START,
126 DP_PPDU_STATUS_DONE,
127 };
128
129 struct ath11k_mon_data {
130 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
131 struct hal_rx_mon_ppdu_info mon_ppdu_info;
132
133 u32 mon_ppdu_status;
134 u32 mon_last_buf_cookie;
135 u64 mon_last_linkdesc_paddr;
136 u16 chan_noise_floor;
137
138 struct ath11k_pdev_mon_stats rx_mon_stats;
139 /* lock for monitor data */
140 spinlock_t mon_lock;
141 struct sk_buff_head rx_status_q;
142 };
143
144 struct ath11k_pdev_dp {
145 u32 mac_id;
146 atomic_t num_tx_pending;
147 wait_queue_head_t tx_empty_waitq;
148 struct dp_rxdma_ring rx_refill_buf_ring;
149 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV];
150 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV];
151 struct dp_srng rxdma_mon_dst_ring;
152 struct dp_srng rxdma_mon_desc_ring;
153
154 struct dp_rxdma_ring rxdma_mon_buf_ring;
155 struct dp_rxdma_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV];
156 struct ieee80211_rx_status rx_status;
157 struct ath11k_mon_data mon_data;
158 };
159
160 #define DP_NUM_CLIENTS_MAX 64
161 #define DP_AVG_TIDS_PER_CLIENT 2
162 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT)
163 #define DP_AVG_MSDUS_PER_FLOW 128
164 #define DP_AVG_FLOWS_PER_TID 2
165 #define DP_AVG_MPDUS_PER_TID_MAX 128
166 #define DP_AVG_MSDUS_PER_MPDU 4
167
168 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */
169
170 #define DP_BA_WIN_SZ_MAX 256
171
172 #define DP_TCL_NUM_RING_MAX 3
173
174 #define DP_IDLE_SCATTER_BUFS_MAX 16
175
176 #define DP_WBM_RELEASE_RING_SIZE 64
177 #define DP_TCL_DATA_RING_SIZE 512
178 #define DP_TX_COMP_RING_SIZE 32768
179 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE
180 #define DP_TCL_CMD_RING_SIZE 32
181 #define DP_TCL_STATUS_RING_SIZE 32
182 #define DP_REO_DST_RING_MAX 4
183 #define DP_REO_DST_RING_SIZE 2048
184 #define DP_REO_REINJECT_RING_SIZE 32
185 #define DP_RX_RELEASE_RING_SIZE 1024
186 #define DP_REO_EXCEPTION_RING_SIZE 128
187 #define DP_REO_CMD_RING_SIZE 128
188 #define DP_REO_STATUS_RING_SIZE 2048
189 #define DP_RXDMA_BUF_RING_SIZE 4096
190 #define DP_RXDMA_REFILL_RING_SIZE 2048
191 #define DP_RXDMA_ERR_DST_RING_SIZE 1024
192 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024
193 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096
194 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048
195 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096
196
197 #define DP_RX_BUFFER_SIZE 2048
198 #define DP_RX_BUFFER_ALIGN_SIZE 128
199
200 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)
201 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18)
202
203 #define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0)
204 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1)
205
206 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)
207 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
208 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
209
210 #define ATH11K_SHADOW_DP_TIMER_INTERVAL 20
211 #define ATH11K_SHADOW_CTRL_TIMER_INTERVAL 10
212
213 struct ath11k_hp_update_timer {
214 struct timer_list timer;
215 bool started;
216 bool init;
217 u32 tx_num;
218 u32 timer_tx_num;
219 u32 ring_id;
220 u32 interval;
221 struct ath11k_base *ab;
222 };
223
224 struct ath11k_dp {
225 struct ath11k_base *ab;
226 enum ath11k_htc_ep_id eid;
227 struct completion htt_tgt_version_received;
228 u8 htt_tgt_ver_major;
229 u8 htt_tgt_ver_minor;
230 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
231 struct dp_srng wbm_idle_ring;
232 struct dp_srng wbm_desc_rel_ring;
233 struct dp_srng tcl_cmd_ring;
234 struct dp_srng tcl_status_ring;
235 struct dp_srng reo_reinject_ring;
236 struct dp_srng rx_rel_ring;
237 struct dp_srng reo_except_ring;
238 struct dp_srng reo_cmd_ring;
239 struct dp_srng reo_status_ring;
240 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX];
241 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX];
242 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX];
243 struct list_head reo_cmd_list;
244 struct list_head reo_cmd_cache_flush_list;
245 u32 reo_cmd_cache_flush_count;
246 /**
247 * protects access to below fields,
248 * - reo_cmd_list
249 * - reo_cmd_cache_flush_list
250 * - reo_cmd_cache_flush_count
251 */
252 spinlock_t reo_cmd_lock;
253 struct ath11k_hp_update_timer reo_cmd_timer;
254 struct ath11k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX];
255 };
256
257 /* HTT definitions */
258
259 #define HTT_TCL_META_DATA_TYPE BIT(0)
260 #define HTT_TCL_META_DATA_VALID_HTT BIT(1)
261
262 /* vdev meta data */
263 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2)
264 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10)
265 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12)
266
267 /* peer meta data */
268 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2)
269
270 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8
271
272 /* HTT tx completion is overlayed in wbm_release_ring */
273 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9)
274 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13)
275 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13)
276
277 #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24)
278
279 struct htt_tx_wbm_completion {
280 u32 info0;
281 u32 info1;
282 u32 info2;
283 u32 info3;
284 } __packed;
285
286 enum htt_h2t_msg_type {
287 HTT_H2T_MSG_TYPE_VERSION_REQ = 0,
288 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb,
289 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc,
290 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10,
291 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11,
292 };
293
294 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0)
295
296 struct htt_ver_req_cmd {
297 u32 ver_reg_info;
298 } __packed;
299
300 enum htt_srng_ring_type {
301 HTT_HW_TO_SW_RING,
302 HTT_SW_TO_HW_RING,
303 HTT_SW_TO_SW_RING,
304 };
305
306 enum htt_srng_ring_id {
307 HTT_RXDMA_HOST_BUF_RING,
308 HTT_RXDMA_MONITOR_STATUS_RING,
309 HTT_RXDMA_MONITOR_BUF_RING,
310 HTT_RXDMA_MONITOR_DESC_RING,
311 HTT_RXDMA_MONITOR_DEST_RING,
312 HTT_HOST1_TO_FW_RXBUF_RING,
313 HTT_HOST2_TO_FW_RXBUF_RING,
314 HTT_RXDMA_NON_MONITOR_DEST_RING,
315 };
316
317 /* host -> target HTT_SRING_SETUP message
318 *
319 * After target is booted up, Host can send SRING setup message for
320 * each host facing LMAC SRING. Target setups up HW registers based
321 * on setup message and confirms back to Host if response_required is set.
322 * Host should wait for confirmation message before sending new SRING
323 * setup message
324 *
325 * The message would appear as follows:
326 *
327 * |31 24|23 20|19|18 16|15|14 8|7 0|
328 * |--------------- +-----------------+----------------+------------------|
329 * | ring_type | ring_id | pdev_id | msg_type |
330 * |----------------------------------------------------------------------|
331 * | ring_base_addr_lo |
332 * |----------------------------------------------------------------------|
333 * | ring_base_addr_hi |
334 * |----------------------------------------------------------------------|
335 * |ring_misc_cfg_flag|ring_entry_size| ring_size |
336 * |----------------------------------------------------------------------|
337 * | ring_head_offset32_remote_addr_lo |
338 * |----------------------------------------------------------------------|
339 * | ring_head_offset32_remote_addr_hi |
340 * |----------------------------------------------------------------------|
341 * | ring_tail_offset32_remote_addr_lo |
342 * |----------------------------------------------------------------------|
343 * | ring_tail_offset32_remote_addr_hi |
344 * |----------------------------------------------------------------------|
345 * | ring_msi_addr_lo |
346 * |----------------------------------------------------------------------|
347 * | ring_msi_addr_hi |
348 * |----------------------------------------------------------------------|
349 * | ring_msi_data |
350 * |----------------------------------------------------------------------|
351 * | intr_timer_th |IM| intr_batch_counter_th |
352 * |----------------------------------------------------------------------|
353 * | reserved |RR|PTCF| intr_low_threshold |
354 * |----------------------------------------------------------------------|
355 * Where
356 * IM = sw_intr_mode
357 * RR = response_required
358 * PTCF = prefetch_timer_cfg
359 *
360 * The message is interpreted as follows:
361 * dword0 - b'0:7 - msg_type: This will be set to
362 * HTT_H2T_MSG_TYPE_SRING_SETUP
363 * b'8:15 - pdev_id:
364 * 0 (for rings at SOC/UMAC level),
365 * 1/2/3 mac id (for rings at LMAC level)
366 * b'16:23 - ring_id: identify which ring is to setup,
367 * more details can be got from enum htt_srng_ring_id
368 * b'24:31 - ring_type: identify type of host rings,
369 * more details can be got from enum htt_srng_ring_type
370 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address
371 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address
372 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words
373 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units
374 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and
375 * SW_TO_HW_RING.
376 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs.
377 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo:
378 * Lower 32 bits of memory address of the remote variable
379 * storing the 4-byte word offset that identifies the head
380 * element within the ring.
381 * (The head offset variable has type u32.)
382 * Valid for HW_TO_SW and SW_TO_SW rings.
383 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi:
384 * Upper 32 bits of memory address of the remote variable
385 * storing the 4-byte word offset that identifies the head
386 * element within the ring.
387 * (The head offset variable has type u32.)
388 * Valid for HW_TO_SW and SW_TO_SW rings.
389 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo:
390 * Lower 32 bits of memory address of the remote variable
391 * storing the 4-byte word offset that identifies the tail
392 * element within the ring.
393 * (The tail offset variable has type u32.)
394 * Valid for HW_TO_SW and SW_TO_SW rings.
395 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi:
396 * Upper 32 bits of memory address of the remote variable
397 * storing the 4-byte word offset that identifies the tail
398 * element within the ring.
399 * (The tail offset variable has type u32.)
400 * Valid for HW_TO_SW and SW_TO_SW rings.
401 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address
402 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
403 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address
404 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
405 * dword10 - b'0:31 - ring_msi_data: MSI data
406 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs
407 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
408 * dword11 - b'0:14 - intr_batch_counter_th:
409 * batch counter threshold is in units of 4-byte words.
410 * HW internally maintains and increments batch count.
411 * (see SRING spec for detail description).
412 * When batch count reaches threshold value, an interrupt
413 * is generated by HW.
414 * b'15 - sw_intr_mode:
415 * This configuration shall be static.
416 * Only programmed at power up.
417 * 0: generate pulse style sw interrupts
418 * 1: generate level style sw interrupts
419 * b'16:31 - intr_timer_th:
420 * The timer init value when timer is idle or is
421 * initialized to start downcounting.
422 * In 8us units (to cover a range of 0 to 524 ms)
423 * dword12 - b'0:15 - intr_low_threshold:
424 * Used only by Consumer ring to generate ring_sw_int_p.
425 * Ring entries low threshold water mark, that is used
426 * in combination with the interrupt timer as well as
427 * the clearing of the level interrupt.
428 * b'16:18 - prefetch_timer_cfg:
429 * Used only by Consumer ring to set timer mode to
430 * support Application prefetch handling.
431 * The external tail offset/pointer will be updated
432 * at following intervals:
433 * 3'b000: (Prefetch feature disabled; used only for debug)
434 * 3'b001: 1 usec
435 * 3'b010: 4 usec
436 * 3'b011: 8 usec (default)
437 * 3'b100: 16 usec
438 * Others: Reserverd
439 * b'19 - response_required:
440 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response
441 * b'20:31 - reserved: reserved for future use
442 */
443
444 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
445 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8)
446 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16)
447 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24)
448
449 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0)
450 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16)
451 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25)
452 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27)
453 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28)
454 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29)
455
456 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0)
457 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15)
458 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16)
459
460 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0)
461 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG BIT(16)
462 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19)
463
464 struct htt_srng_setup_cmd {
465 u32 info0;
466 u32 ring_base_addr_lo;
467 u32 ring_base_addr_hi;
468 u32 info1;
469 u32 ring_head_off32_remote_addr_lo;
470 u32 ring_head_off32_remote_addr_hi;
471 u32 ring_tail_off32_remote_addr_lo;
472 u32 ring_tail_off32_remote_addr_hi;
473 u32 ring_msi_addr_lo;
474 u32 ring_msi_addr_hi;
475 u32 msi_data;
476 u32 intr_info;
477 u32 info2;
478 } __packed;
479
480 /* host -> target FW PPDU_STATS config message
481 *
482 * @details
483 * The following field definitions describe the format of the HTT host
484 * to target FW for PPDU_STATS_CFG msg.
485 * The message allows the host to configure the PPDU_STATS_IND messages
486 * produced by the target.
487 *
488 * |31 24|23 16|15 8|7 0|
489 * |-----------------------------------------------------------|
490 * | REQ bit mask | pdev_mask | msg type |
491 * |-----------------------------------------------------------|
492 * Header fields:
493 * - MSG_TYPE
494 * Bits 7:0
495 * Purpose: identifies this is a req to configure ppdu_stats_ind from target
496 * Value: 0x11
497 * - PDEV_MASK
498 * Bits 8:15
499 * Purpose: identifies which pdevs this PPDU stats configuration applies to
500 * Value: This is a overloaded field, refer to usage and interpretation of
501 * PDEV in interface document.
502 * Bit 8 : Reserved for SOC stats
503 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
504 * Indicates MACID_MASK in DBS
505 * - REQ_TLV_BIT_MASK
506 * Bits 16:31
507 * Purpose: each set bit indicates the corresponding PPDU stats TLV type
508 * needs to be included in the target's PPDU_STATS_IND messages.
509 * Value: refer htt_ppdu_stats_tlv_tag_t <<<???
510 *
511 */
512
513 struct htt_ppdu_stats_cfg_cmd {
514 u32 msg;
515 } __packed;
516
517 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0)
518 #define HTT_PPDU_STATS_CFG_SOC_STATS BIT(8)
519 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 9)
520 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16)
521
522 enum htt_ppdu_stats_tag_type {
523 HTT_PPDU_STATS_TAG_COMMON,
524 HTT_PPDU_STATS_TAG_USR_COMMON,
525 HTT_PPDU_STATS_TAG_USR_RATE,
526 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64,
527 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256,
528 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS,
529 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON,
530 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64,
531 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256,
532 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS,
533 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH,
534 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY,
535 HTT_PPDU_STATS_TAG_INFO,
536 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD,
537
538 /* New TLV's are added above to this line */
539 HTT_PPDU_STATS_TAG_MAX,
540 };
541
542 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \
543 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \
544 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \
545 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \
546 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \
547 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \
548 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \
549 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY))
550
551 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \
552 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \
553 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \
554 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \
555 BIT(HTT_PPDU_STATS_TAG_INFO) | \
556 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \
557 HTT_PPDU_STATS_TAG_DEFAULT)
558
559 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message
560 *
561 * details:
562 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to
563 * configure RXDMA rings.
564 * The configuration is per ring based and includes both packet subtypes
565 * and PPDU/MPDU TLVs.
566 *
567 * The message would appear as follows:
568 *
569 * |31 26|25|24|23 16|15 8|7 0|
570 * |-----------------+----------------+----------------+---------------|
571 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type |
572 * |-------------------------------------------------------------------|
573 * | rsvd2 | ring_buffer_size |
574 * |-------------------------------------------------------------------|
575 * | packet_type_enable_flags_0 |
576 * |-------------------------------------------------------------------|
577 * | packet_type_enable_flags_1 |
578 * |-------------------------------------------------------------------|
579 * | packet_type_enable_flags_2 |
580 * |-------------------------------------------------------------------|
581 * | packet_type_enable_flags_3 |
582 * |-------------------------------------------------------------------|
583 * | tlv_filter_in_flags |
584 * |-------------------------------------------------------------------|
585 * Where:
586 * PS = pkt_swap
587 * SS = status_swap
588 * The message is interpreted as follows:
589 * dword0 - b'0:7 - msg_type: This will be set to
590 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG
591 * b'8:15 - pdev_id:
592 * 0 (for rings at SOC/UMAC level),
593 * 1/2/3 mac id (for rings at LMAC level)
594 * b'16:23 - ring_id : Identify the ring to configure.
595 * More details can be got from enum htt_srng_ring_id
596 * b'24 - status_swap: 1 is to swap status TLV
597 * b'25 - pkt_swap: 1 is to swap packet TLV
598 * b'26:31 - rsvd1: reserved for future use
599 * dword1 - b'0:16 - ring_buffer_size: size of bufferes referenced by rx ring,
600 * in byte units.
601 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
602 * - b'16:31 - rsvd2: Reserved for future use
603 * dword2 - b'0:31 - packet_type_enable_flags_0:
604 * Enable MGMT packet from 0b0000 to 0b1001
605 * bits from low to high: FP, MD, MO - 3 bits
606 * FP: Filter_Pass
607 * MD: Monitor_Direct
608 * MO: Monitor_Other
609 * 10 mgmt subtypes * 3 bits -> 30 bits
610 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs
611 * dword3 - b'0:31 - packet_type_enable_flags_1:
612 * Enable MGMT packet from 0b1010 to 0b1111
613 * bits from low to high: FP, MD, MO - 3 bits
614 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs
615 * dword4 - b'0:31 - packet_type_enable_flags_2:
616 * Enable CTRL packet from 0b0000 to 0b1001
617 * bits from low to high: FP, MD, MO - 3 bits
618 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs
619 * dword5 - b'0:31 - packet_type_enable_flags_3:
620 * Enable CTRL packet from 0b1010 to 0b1111,
621 * MCAST_DATA, UCAST_DATA, NULL_DATA
622 * bits from low to high: FP, MD, MO - 3 bits
623 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs
624 * dword6 - b'0:31 - tlv_filter_in_flags:
625 * Filter in Attention/MPDU/PPDU/Header/User tlvs
626 * Refer to CFG_TLV_FILTER_IN_FLAG defs
627 */
628
629 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
630 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
631 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)
632 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)
633 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)
634
635 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0)
636
637 enum htt_rx_filter_tlv_flags {
638 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0),
639 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1),
640 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2),
641 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3),
642 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4),
643 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5),
644 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6),
645 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7),
646 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8),
647 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9),
648 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10),
649 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11),
650 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12),
651 };
652
653 enum htt_rx_mgmt_pkt_filter_tlv_flags0 {
654 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0),
655 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1),
656 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2),
657 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3),
658 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4),
659 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5),
660 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6),
661 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7),
662 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8),
663 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9),
664 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10),
665 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11),
666 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12),
667 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13),
668 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14),
669 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15),
670 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16),
671 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17),
672 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18),
673 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19),
674 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20),
675 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21),
676 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22),
677 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23),
678 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24),
679 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25),
680 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26),
681 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27),
682 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28),
683 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29),
684 };
685
686 enum htt_rx_mgmt_pkt_filter_tlv_flags1 {
687 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0),
688 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1),
689 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2),
690 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3),
691 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4),
692 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5),
693 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6),
694 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7),
695 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8),
696 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9),
697 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10),
698 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11),
699 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12),
700 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13),
701 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14),
702 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15),
703 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16),
704 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17),
705 };
706
707 enum htt_rx_ctrl_pkt_filter_tlv_flags2 {
708 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0),
709 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1),
710 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2),
711 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3),
712 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4),
713 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5),
714 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6),
715 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7),
716 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8),
717 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9),
718 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10),
719 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11),
720 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12),
721 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13),
722 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14),
723 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15),
724 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16),
725 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17),
726 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18),
727 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19),
728 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20),
729 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21),
730 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22),
731 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23),
732 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24),
733 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25),
734 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26),
735 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27),
736 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28),
737 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29),
738 };
739
740 enum htt_rx_ctrl_pkt_filter_tlv_flags3 {
741 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0),
742 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1),
743 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2),
744 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3),
745 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4),
746 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5),
747 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6),
748 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7),
749 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8),
750 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9),
751 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10),
752 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11),
753 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12),
754 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13),
755 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14),
756 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15),
757 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16),
758 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17),
759 };
760
761 enum htt_rx_data_pkt_filter_tlv_flasg3 {
762 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18),
763 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19),
764 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20),
765 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21),
766 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22),
767 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23),
768 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24),
769 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25),
770 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26),
771 };
772
773 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \
774 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
775 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
776 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
777 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
778 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
779 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
780 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
781 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
782 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
783
784 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \
785 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
786 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
787 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
788 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
789 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
790 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
791 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
792 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
793 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
794
795 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \
796 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
797 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
798 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
799 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
800 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
801 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
802 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
803 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
804 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
805
806 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
807 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
808 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
809 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
810 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
811
812 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
813 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
814 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
815 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
816 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
817
818 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
819 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
820 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
821 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
822 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
823
824 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
825 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
826 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
827
828 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
829 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
830 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
831
832 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
833 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
834 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
835
836 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
837 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
838 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
839 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
840 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
841 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
842
843 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
844 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
845 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
846 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
847 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
848 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
849
850 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
851 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
852 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
853 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
854 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
855 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
856
857 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
858 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
859 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
860
861 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
862 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
863 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
864
865 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
866 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
867 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
868
869 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \
870 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \
871 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
872
873 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \
874 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \
875 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
876
877 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \
878 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \
879 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
880
881 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \
882 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \
883 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
884
885 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \
886 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \
887 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
888 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
889 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
890 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
891 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
892 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
893 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
894
895 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \
896 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \
897 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
898 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
899 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
900 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
901 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
902 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
903 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
904
905 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3
906
907 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3
908
909 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3
910
911 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3
912
913 #define HTT_RX_MON_FILTER_TLV_FLAGS \
914 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
915 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
916 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
917 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
918 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
919 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
920
921 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \
922 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
923 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
924 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
925 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
926 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
927 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
928
929 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \
930 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
931 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \
932 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
933 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \
934 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \
935 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \
936 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \
937 HTT_RX_FILTER_TLV_FLAGS_ATTENTION)
938
939 struct htt_rx_ring_selection_cfg_cmd {
940 u32 info0;
941 u32 info1;
942 u32 pkt_type_en_flags0;
943 u32 pkt_type_en_flags1;
944 u32 pkt_type_en_flags2;
945 u32 pkt_type_en_flags3;
946 u32 rx_filter_tlv;
947 } __packed;
948
949 struct htt_rx_ring_tlv_filter {
950 u32 rx_filter; /* see htt_rx_filter_tlv_flags */
951 u32 pkt_filter_flags0; /* MGMT */
952 u32 pkt_filter_flags1; /* MGMT */
953 u32 pkt_filter_flags2; /* CTRL */
954 u32 pkt_filter_flags3; /* DATA */
955 };
956
957 /* HTT message target->host */
958
959 enum htt_t2h_msg_type {
960 HTT_T2H_MSG_TYPE_VERSION_CONF,
961 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3,
962 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
963 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5,
964 HTT_T2H_MSG_TYPE_PKTLOG = 0x8,
965 HTT_T2H_MSG_TYPE_SEC_IND = 0xb,
966 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e,
967 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f,
968 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d,
969 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c,
970 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24,
971 };
972
973 #define HTT_TARGET_VERSION_MAJOR 3
974
975 #define HTT_T2H_MSG_TYPE GENMASK(7, 0)
976 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8)
977 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16)
978
979 struct htt_t2h_version_conf_msg {
980 u32 version;
981 } __packed;
982
983 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8)
984 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16)
985 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0)
986 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16)
987 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0)
988 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16)
989 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16
990
991 struct htt_t2h_peer_map_event {
992 u32 info;
993 u32 mac_addr_l32;
994 u32 info1;
995 u32 info2;
996 } __packed;
997
998 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID
999 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID
1000 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \
1001 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16
1002 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M
1003 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S
1004
1005 struct htt_t2h_peer_unmap_event {
1006 u32 info;
1007 u32 mac_addr_l32;
1008 u32 info1;
1009 } __packed;
1010
1011 struct htt_resp_msg {
1012 union {
1013 struct htt_t2h_version_conf_msg version_msg;
1014 struct htt_t2h_peer_map_event peer_map_ev;
1015 struct htt_t2h_peer_unmap_event peer_unmap_ev;
1016 };
1017 } __packed;
1018
1019 #define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8)
1020 #define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16)
1021 #define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24)
1022
1023 #define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0)
1024 #define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16)
1025
1026 #define HTT_BACKPRESSURE_UMAC_RING_TYPE 0
1027 #define HTT_BACKPRESSURE_LMAC_RING_TYPE 1
1028
1029 enum htt_backpressure_umac_ringid {
1030 HTT_SW_RING_IDX_REO_REO2SW1_RING,
1031 HTT_SW_RING_IDX_REO_REO2SW2_RING,
1032 HTT_SW_RING_IDX_REO_REO2SW3_RING,
1033 HTT_SW_RING_IDX_REO_REO2SW4_RING,
1034 HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING,
1035 HTT_SW_RING_IDX_REO_REO2TCL_RING,
1036 HTT_SW_RING_IDX_REO_REO2FW_RING,
1037 HTT_SW_RING_IDX_REO_REO_RELEASE_RING,
1038 HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING,
1039 HTT_SW_RING_IDX_TCL_TCL2TQM_RING,
1040 HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING,
1041 HTT_SW_RING_IDX_WBM_REO_RELEASE_RING,
1042 HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING,
1043 HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING,
1044 HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING,
1045 HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING,
1046 HTT_SW_RING_IDX_REO_REO_CMD_RING,
1047 HTT_SW_RING_IDX_REO_REO_STATUS_RING,
1048 HTT_SW_UMAC_RING_IDX_MAX,
1049 };
1050
1051 enum htt_backpressure_lmac_ringid {
1052 HTT_SW_RING_IDX_FW2RXDMA_BUF_RING,
1053 HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING,
1054 HTT_SW_RING_IDX_FW2RXDMA_LINK_RING,
1055 HTT_SW_RING_IDX_SW2RXDMA_BUF_RING,
1056 HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING,
1057 HTT_SW_RING_IDX_RXDMA2FW_RING,
1058 HTT_SW_RING_IDX_RXDMA2SW_RING,
1059 HTT_SW_RING_IDX_RXDMA2RELEASE_RING,
1060 HTT_SW_RING_IDX_RXDMA2REO_RING,
1061 HTT_SW_RING_IDX_MONITOR_STATUS_RING,
1062 HTT_SW_RING_IDX_MONITOR_BUF_RING,
1063 HTT_SW_RING_IDX_MONITOR_DESC_RING,
1064 HTT_SW_RING_IDX_MONITOR_DEST_RING,
1065 HTT_SW_LMAC_RING_IDX_MAX,
1066 };
1067
1068 /* ppdu stats
1069 *
1070 * @details
1071 * The following field definitions describe the format of the HTT target
1072 * to host ppdu stats indication message.
1073 *
1074 *
1075 * |31 16|15 12|11 10|9 8|7 0 |
1076 * |----------------------------------------------------------------------|
1077 * | payload_size | rsvd |pdev_id|mac_id | msg type |
1078 * |----------------------------------------------------------------------|
1079 * | ppdu_id |
1080 * |----------------------------------------------------------------------|
1081 * | Timestamp in us |
1082 * |----------------------------------------------------------------------|
1083 * | reserved |
1084 * |----------------------------------------------------------------------|
1085 * | type-specific stats info |
1086 * | (see htt_ppdu_stats.h) |
1087 * |----------------------------------------------------------------------|
1088 * Header fields:
1089 * - MSG_TYPE
1090 * Bits 7:0
1091 * Purpose: Identifies this is a PPDU STATS indication
1092 * message.
1093 * Value: 0x1d
1094 * - mac_id
1095 * Bits 9:8
1096 * Purpose: mac_id of this ppdu_id
1097 * Value: 0-3
1098 * - pdev_id
1099 * Bits 11:10
1100 * Purpose: pdev_id of this ppdu_id
1101 * Value: 0-3
1102 * 0 (for rings at SOC level),
1103 * 1/2/3 PDEV -> 0/1/2
1104 * - payload_size
1105 * Bits 31:16
1106 * Purpose: total tlv size
1107 * Value: payload_size in bytes
1108 */
1109
1110 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)
1111 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)
1112
1113 struct ath11k_htt_ppdu_stats_msg {
1114 u32 info;
1115 u32 ppdu_id;
1116 u32 timestamp;
1117 u32 rsvd;
1118 u8 data[0];
1119 } __packed;
1120
1121 struct htt_tlv {
1122 u32 header;
1123 u8 value[0];
1124 } __packed;
1125
1126 #define HTT_TLV_TAG GENMASK(11, 0)
1127 #define HTT_TLV_LEN GENMASK(23, 12)
1128
1129 enum HTT_PPDU_STATS_BW {
1130 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0,
1131 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1,
1132 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2,
1133 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3,
1134 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4,
1135 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */
1136 HTT_PPDU_STATS_BANDWIDTH_DYN = 6,
1137 };
1138
1139 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0)
1140 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8)
1141 /* bw - HTT_PPDU_STATS_BW */
1142 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16)
1143
1144 struct htt_ppdu_stats_common {
1145 u32 ppdu_id;
1146 u16 sched_cmdid;
1147 u8 ring_id;
1148 u8 num_users;
1149 u32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/
1150 u32 chain_mask;
1151 u32 fes_duration_us; /* frame exchange sequence */
1152 u32 ppdu_sch_eval_start_tstmp_us;
1153 u32 ppdu_sch_end_tstmp_us;
1154 u32 ppdu_start_tstmp_us;
1155 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted
1156 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted
1157 */
1158 u16 phy_mode;
1159 u16 bw_mhz;
1160 } __packed;
1161
1162 enum htt_ppdu_stats_gi {
1163 HTT_PPDU_STATS_SGI_0_8_US,
1164 HTT_PPDU_STATS_SGI_0_4_US,
1165 HTT_PPDU_STATS_SGI_1_6_US,
1166 HTT_PPDU_STATS_SGI_3_2_US,
1167 };
1168
1169 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0)
1170 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4)
1171
1172 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0)
1173 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1)
1174
1175 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0)
1176 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2)
1177 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3)
1178 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4)
1179 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8)
1180 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12)
1181 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16)
1182 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20)
1183 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24)
1184 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28)
1185 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29)
1186
1187 #define HTT_USR_RATE_PREAMBLE(_val) \
1188 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val)
1189 #define HTT_USR_RATE_BW(_val) \
1190 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val)
1191 #define HTT_USR_RATE_NSS(_val) \
1192 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val)
1193 #define HTT_USR_RATE_MCS(_val) \
1194 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val)
1195 #define HTT_USR_RATE_GI(_val) \
1196 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val)
1197 #define HTT_USR_RATE_DCM(_val) \
1198 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val)
1199
1200 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0)
1201 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2)
1202 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3)
1203 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4)
1204 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8)
1205 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12)
1206 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16)
1207 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20)
1208 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24)
1209 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28)
1210 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29)
1211
1212 struct htt_ppdu_stats_user_rate {
1213 u8 tid_num;
1214 u8 reserved0;
1215 u16 sw_peer_id;
1216 u32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/
1217 u16 ru_end;
1218 u16 ru_start;
1219 u16 resp_ru_end;
1220 u16 resp_ru_start;
1221 u32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */
1222 u32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */
1223 /* Note: resp_rate_info is only valid for if resp_type is UL */
1224 u32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */
1225 } __packed;
1226
1227 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0)
1228 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8)
1229 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9)
1230 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11)
1231 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14)
1232 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16)
1233
1234 #define HTT_TX_INFO_IS_AMSDU(_flags) \
1235 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags)
1236 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \
1237 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags)
1238 #define HTT_TX_INFO_RATECODE(_flags) \
1239 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags)
1240 #define HTT_TX_INFO_PEERID(_flags) \
1241 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags)
1242
1243 struct htt_tx_ppdu_stats_info {
1244 struct htt_tlv tlv_hdr;
1245 u32 tx_success_bytes;
1246 u32 tx_retry_bytes;
1247 u32 tx_failed_bytes;
1248 u32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */
1249 u16 tx_success_msdus;
1250 u16 tx_retry_msdus;
1251 u16 tx_failed_msdus;
1252 u16 tx_duration; /* united in us */
1253 } __packed;
1254
1255 enum htt_ppdu_stats_usr_compln_status {
1256 HTT_PPDU_STATS_USER_STATUS_OK,
1257 HTT_PPDU_STATS_USER_STATUS_FILTERED,
1258 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT,
1259 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH,
1260 HTT_PPDU_STATS_USER_STATUS_ABORT,
1261 };
1262
1263 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0)
1264 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4)
1265 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8)
1266 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9)
1267
1268 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \
1269 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val)
1270 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \
1271 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val)
1272 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \
1273 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val)
1274
1275 struct htt_ppdu_stats_usr_cmpltn_cmn {
1276 u8 status;
1277 u8 tid_num;
1278 u16 sw_peer_id;
1279 /* RSSI value of last ack packet (units = dB above noise floor) */
1280 u32 ack_rssi;
1281 u16 mpdu_tried;
1282 u16 mpdu_success;
1283 u32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/
1284 } __packed;
1285
1286 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0)
1287 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9)
1288 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25)
1289
1290 #define HTT_PPDU_STATS_NON_QOS_TID 16
1291
1292 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status {
1293 u32 ppdu_id;
1294 u16 sw_peer_id;
1295 u16 reserved0;
1296 u32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */
1297 u16 current_seq;
1298 u16 start_seq;
1299 u32 success_bytes;
1300 } __packed;
1301
1302 struct htt_ppdu_stats_usr_cmn_array {
1303 struct htt_tlv tlv_hdr;
1304 u32 num_ppdu_stats;
1305 /* tx_ppdu_stats_info is filled by multiple struct htt_tx_ppdu_stats_info
1306 * elements.
1307 * tx_ppdu_stats_info is variable length, with length =
1308 * number_of_ppdu_stats * sizeof (struct htt_tx_ppdu_stats_info)
1309 */
1310 struct htt_tx_ppdu_stats_info tx_ppdu_info[0];
1311 } __packed;
1312
1313 struct htt_ppdu_user_stats {
1314 u16 peer_id;
1315 u32 tlv_flags;
1316 bool is_valid_peer_id;
1317 struct htt_ppdu_stats_user_rate rate;
1318 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn;
1319 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba;
1320 };
1321
1322 #define HTT_PPDU_STATS_MAX_USERS 8
1323 #define HTT_PPDU_DESC_MAX_DEPTH 16
1324
1325 struct htt_ppdu_stats {
1326 struct htt_ppdu_stats_common common;
1327 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS];
1328 };
1329
1330 struct htt_ppdu_stats_info {
1331 u32 ppdu_id;
1332 struct htt_ppdu_stats ppdu_stats;
1333 struct list_head list;
1334 };
1335
1336 /**
1337 * @brief target -> host packet log message
1338 *
1339 * @details
1340 * The following field definitions describe the format of the packet log
1341 * message sent from the target to the host.
1342 * The message consists of a 4-octet header,followed by a variable number
1343 * of 32-bit character values.
1344 *
1345 * |31 16|15 12|11 10|9 8|7 0|
1346 * |------------------------------------------------------------------|
1347 * | payload_size | rsvd |pdev_id|mac_id| msg type |
1348 * |------------------------------------------------------------------|
1349 * | payload |
1350 * |------------------------------------------------------------------|
1351 * - MSG_TYPE
1352 * Bits 7:0
1353 * Purpose: identifies this as a pktlog message
1354 * Value: HTT_T2H_MSG_TYPE_PKTLOG
1355 * - mac_id
1356 * Bits 9:8
1357 * Purpose: identifies which MAC/PHY instance generated this pktlog info
1358 * Value: 0-3
1359 * - pdev_id
1360 * Bits 11:10
1361 * Purpose: pdev_id
1362 * Value: 0-3
1363 * 0 (for rings at SOC level),
1364 * 1/2/3 PDEV -> 0/1/2
1365 * - payload_size
1366 * Bits 31:16
1367 * Purpose: explicitly specify the payload size
1368 * Value: payload size in bytes (payload size is a multiple of 4 bytes)
1369 */
1370 struct htt_pktlog_msg {
1371 u32 hdr;
1372 u8 payload[0];
1373 };
1374
1375 /**
1376 * @brief host -> target FW extended statistics retrieve
1377 *
1378 * @details
1379 * The following field definitions describe the format of the HTT host
1380 * to target FW extended stats retrieve message.
1381 * The message specifies the type of stats the host wants to retrieve.
1382 *
1383 * |31 24|23 16|15 8|7 0|
1384 * |-----------------------------------------------------------|
1385 * | reserved | stats type | pdev_mask | msg type |
1386 * |-----------------------------------------------------------|
1387 * | config param [0] |
1388 * |-----------------------------------------------------------|
1389 * | config param [1] |
1390 * |-----------------------------------------------------------|
1391 * | config param [2] |
1392 * |-----------------------------------------------------------|
1393 * | config param [3] |
1394 * |-----------------------------------------------------------|
1395 * | reserved |
1396 * |-----------------------------------------------------------|
1397 * | cookie LSBs |
1398 * |-----------------------------------------------------------|
1399 * | cookie MSBs |
1400 * |-----------------------------------------------------------|
1401 * Header fields:
1402 * - MSG_TYPE
1403 * Bits 7:0
1404 * Purpose: identifies this is a extended stats upload request message
1405 * Value: 0x10
1406 * - PDEV_MASK
1407 * Bits 8:15
1408 * Purpose: identifies the mask of PDEVs to retrieve stats from
1409 * Value: This is a overloaded field, refer to usage and interpretation of
1410 * PDEV in interface document.
1411 * Bit 8 : Reserved for SOC stats
1412 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
1413 * Indicates MACID_MASK in DBS
1414 * - STATS_TYPE
1415 * Bits 23:16
1416 * Purpose: identifies which FW statistics to upload
1417 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h)
1418 * - Reserved
1419 * Bits 31:24
1420 * - CONFIG_PARAM [0]
1421 * Bits 31:0
1422 * Purpose: give an opaque configuration value to the specified stats type
1423 * Value: stats-type specific configuration value
1424 * Refer to htt_stats.h for interpretation for each stats sub_type
1425 * - CONFIG_PARAM [1]
1426 * Bits 31:0
1427 * Purpose: give an opaque configuration value to the specified stats type
1428 * Value: stats-type specific configuration value
1429 * Refer to htt_stats.h for interpretation for each stats sub_type
1430 * - CONFIG_PARAM [2]
1431 * Bits 31:0
1432 * Purpose: give an opaque configuration value to the specified stats type
1433 * Value: stats-type specific configuration value
1434 * Refer to htt_stats.h for interpretation for each stats sub_type
1435 * - CONFIG_PARAM [3]
1436 * Bits 31:0
1437 * Purpose: give an opaque configuration value to the specified stats type
1438 * Value: stats-type specific configuration value
1439 * Refer to htt_stats.h for interpretation for each stats sub_type
1440 * - Reserved [31:0] for future use.
1441 * - COOKIE_LSBS
1442 * Bits 31:0
1443 * Purpose: Provide a mechanism to match a target->host stats confirmation
1444 * message with its preceding host->target stats request message.
1445 * Value: LSBs of the opaque cookie specified by the host-side requestor
1446 * - COOKIE_MSBS
1447 * Bits 31:0
1448 * Purpose: Provide a mechanism to match a target->host stats confirmation
1449 * message with its preceding host->target stats request message.
1450 * Value: MSBs of the opaque cookie specified by the host-side requestor
1451 */
1452
1453 struct htt_ext_stats_cfg_hdr {
1454 u8 msg_type;
1455 u8 pdev_mask;
1456 u8 stats_type;
1457 u8 reserved;
1458 } __packed;
1459
1460 struct htt_ext_stats_cfg_cmd {
1461 struct htt_ext_stats_cfg_hdr hdr;
1462 u32 cfg_param0;
1463 u32 cfg_param1;
1464 u32 cfg_param2;
1465 u32 cfg_param3;
1466 u32 reserved;
1467 u32 cookie_lsb;
1468 u32 cookie_msb;
1469 } __packed;
1470
1471 /* htt stats config default params */
1472 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0
1473 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff
1474 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff
1475 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff
1476 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff
1477 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff
1478 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00
1479 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00
1480
1481 /* HTT_DBG_EXT_STATS_PEER_INFO
1482 * PARAMS:
1483 * @config_param0:
1484 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request
1485 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t
1486 * [Bit31 : Bit16] sw_peer_id
1487 * @config_param1:
1488 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum)
1489 * 0 bit htt_peer_stats_cmn_tlv
1490 * 1 bit htt_peer_details_tlv
1491 * 2 bit htt_tx_peer_rate_stats_tlv
1492 * 3 bit htt_rx_peer_rate_stats_tlv
1493 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv
1494 * 5 bit htt_rx_tid_stats_tlv
1495 * 6 bit htt_msdu_flow_stats_tlv
1496 * @config_param2: [Bit31 : Bit0] mac_addr31to0
1497 * @config_param3: [Bit15 : Bit0] mac_addr47to32
1498 * [Bit31 : Bit16] reserved
1499 */
1500 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0)
1501 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f
1502
1503 /* Used to set different configs to the specified stats type.*/
1504 struct htt_ext_stats_cfg_params {
1505 u32 cfg0;
1506 u32 cfg1;
1507 u32 cfg2;
1508 u32 cfg3;
1509 };
1510
1511 /**
1512 * @brief target -> host extended statistics upload
1513 *
1514 * @details
1515 * The following field definitions describe the format of the HTT target
1516 * to host stats upload confirmation message.
1517 * The message contains a cookie echoed from the HTT host->target stats
1518 * upload request, which identifies which request the confirmation is
1519 * for, and a single stats can span over multiple HTT stats indication
1520 * due to the HTT message size limitation so every HTT ext stats indication
1521 * will have tag-length-value stats information elements.
1522 * The tag-length header for each HTT stats IND message also includes a
1523 * status field, to indicate whether the request for the stat type in
1524 * question was fully met, partially met, unable to be met, or invalid
1525 * (if the stat type in question is disabled in the target).
1526 * A Done bit 1's indicate the end of the of stats info elements.
1527 *
1528 *
1529 * |31 16|15 12|11|10 8|7 5|4 0|
1530 * |--------------------------------------------------------------|
1531 * | reserved | msg type |
1532 * |--------------------------------------------------------------|
1533 * | cookie LSBs |
1534 * |--------------------------------------------------------------|
1535 * | cookie MSBs |
1536 * |--------------------------------------------------------------|
1537 * | stats entry length | rsvd | D| S | stat type |
1538 * |--------------------------------------------------------------|
1539 * | type-specific stats info |
1540 * | (see htt_stats.h) |
1541 * |--------------------------------------------------------------|
1542 * Header fields:
1543 * - MSG_TYPE
1544 * Bits 7:0
1545 * Purpose: Identifies this is a extended statistics upload confirmation
1546 * message.
1547 * Value: 0x1c
1548 * - COOKIE_LSBS
1549 * Bits 31:0
1550 * Purpose: Provide a mechanism to match a target->host stats confirmation
1551 * message with its preceding host->target stats request message.
1552 * Value: LSBs of the opaque cookie specified by the host-side requestor
1553 * - COOKIE_MSBS
1554 * Bits 31:0
1555 * Purpose: Provide a mechanism to match a target->host stats confirmation
1556 * message with its preceding host->target stats request message.
1557 * Value: MSBs of the opaque cookie specified by the host-side requestor
1558 *
1559 * Stats Information Element tag-length header fields:
1560 * - STAT_TYPE
1561 * Bits 7:0
1562 * Purpose: identifies the type of statistics info held in the
1563 * following information element
1564 * Value: htt_dbg_ext_stats_type
1565 * - STATUS
1566 * Bits 10:8
1567 * Purpose: indicate whether the requested stats are present
1568 * Value: htt_dbg_ext_stats_status
1569 * - DONE
1570 * Bits 11
1571 * Purpose:
1572 * Indicates the completion of the stats entry, this will be the last
1573 * stats conf HTT segment for the requested stats type.
1574 * Value:
1575 * 0 -> the stats retrieval is ongoing
1576 * 1 -> the stats retrieval is complete
1577 * - LENGTH
1578 * Bits 31:16
1579 * Purpose: indicate the stats information size
1580 * Value: This field specifies the number of bytes of stats information
1581 * that follows the element tag-length header.
1582 * It is expected but not required that this length is a multiple of
1583 * 4 bytes.
1584 */
1585
1586 #define HTT_T2H_EXT_STATS_INFO1_DONE BIT(11)
1587 #define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16)
1588
1589 struct ath11k_htt_extd_stats_msg {
1590 u32 info0;
1591 u64 cookie;
1592 u32 info1;
1593 u8 data[0];
1594 } __packed;
1595
1596 struct htt_mac_addr {
1597 u32 mac_addr_l32;
1598 u32 mac_addr_h16;
1599 };
1600
ath11k_dp_get_mac_addr(u32 addr_l32,u16 addr_h16,u8 * addr)1601 static inline void ath11k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr)
1602 {
1603 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
1604 addr_l32 = swab32(addr_l32);
1605 addr_h16 = swab16(addr_h16);
1606 }
1607
1608 memcpy(addr, &addr_l32, 4);
1609 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4);
1610 }
1611
1612 int ath11k_dp_service_srng(struct ath11k_base *ab,
1613 struct ath11k_ext_irq_grp *irq_grp,
1614 int budget);
1615 int ath11k_dp_htt_connect(struct ath11k_dp *dp);
1616 void ath11k_dp_vdev_tx_attach(struct ath11k *ar, struct ath11k_vif *arvif);
1617 void ath11k_dp_free(struct ath11k_base *ab);
1618 int ath11k_dp_alloc(struct ath11k_base *ab);
1619 int ath11k_dp_pdev_alloc(struct ath11k_base *ab);
1620 void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab);
1621 void ath11k_dp_pdev_free(struct ath11k_base *ab);
1622 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id,
1623 int mac_id, enum hal_ring_type ring_type);
1624 int ath11k_dp_peer_setup(struct ath11k *ar, int vdev_id, const u8 *addr);
1625 void ath11k_dp_peer_cleanup(struct ath11k *ar, int vdev_id, const u8 *addr);
1626 void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring);
1627 int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring,
1628 enum hal_ring_type type, int ring_num,
1629 int mac_id, int num_entries);
1630 void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab,
1631 struct dp_link_desc_bank *desc_bank,
1632 u32 ring_type, struct dp_srng *ring);
1633 int ath11k_dp_link_desc_setup(struct ath11k_base *ab,
1634 struct dp_link_desc_bank *link_desc_banks,
1635 u32 ring_type, struct hal_srng *srng,
1636 u32 n_link_desc);
1637 void ath11k_dp_shadow_start_timer(struct ath11k_base *ab,
1638 struct hal_srng *srng,
1639 struct ath11k_hp_update_timer *update_timer);
1640 void ath11k_dp_shadow_stop_timer(struct ath11k_base *ab,
1641 struct ath11k_hp_update_timer *update_timer);
1642 void ath11k_dp_shadow_init_timer(struct ath11k_base *ab,
1643 struct ath11k_hp_update_timer *update_timer,
1644 u32 interval, u32 ring_id);
1645 void ath11k_dp_stop_shadow_timers(struct ath11k_base *ab);
1646
1647 #endif
1648