1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2008 4 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> 5 * 6 * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. 7 */ 8 9 #ifndef _IPU_INTERN_H_ 10 #define _IPU_INTERN_H_ 11 12 #include <linux/dmaengine.h> 13 #include <linux/platform_device.h> 14 #include <linux/interrupt.h> 15 16 /* IPU Common registers */ 17 #define IPU_CONF 0x00 18 #define IPU_CHA_BUF0_RDY 0x04 19 #define IPU_CHA_BUF1_RDY 0x08 20 #define IPU_CHA_DB_MODE_SEL 0x0C 21 #define IPU_CHA_CUR_BUF 0x10 22 #define IPU_FS_PROC_FLOW 0x14 23 #define IPU_FS_DISP_FLOW 0x18 24 #define IPU_TASKS_STAT 0x1C 25 #define IPU_IMA_ADDR 0x20 26 #define IPU_IMA_DATA 0x24 27 #define IPU_INT_CTRL_1 0x28 28 #define IPU_INT_CTRL_2 0x2C 29 #define IPU_INT_CTRL_3 0x30 30 #define IPU_INT_CTRL_4 0x34 31 #define IPU_INT_CTRL_5 0x38 32 #define IPU_INT_STAT_1 0x3C 33 #define IPU_INT_STAT_2 0x40 34 #define IPU_INT_STAT_3 0x44 35 #define IPU_INT_STAT_4 0x48 36 #define IPU_INT_STAT_5 0x4C 37 #define IPU_BRK_CTRL_1 0x50 38 #define IPU_BRK_CTRL_2 0x54 39 #define IPU_BRK_STAT 0x58 40 #define IPU_DIAGB_CTRL 0x5C 41 42 /* IPU_CONF Register bits */ 43 #define IPU_CONF_CSI_EN 0x00000001 44 #define IPU_CONF_IC_EN 0x00000002 45 #define IPU_CONF_ROT_EN 0x00000004 46 #define IPU_CONF_PF_EN 0x00000008 47 #define IPU_CONF_SDC_EN 0x00000010 48 #define IPU_CONF_ADC_EN 0x00000020 49 #define IPU_CONF_DI_EN 0x00000040 50 #define IPU_CONF_DU_EN 0x00000080 51 #define IPU_CONF_PXL_ENDIAN 0x00000100 52 53 /* Image Converter Registers */ 54 #define IC_CONF 0x88 55 #define IC_PRP_ENC_RSC 0x8C 56 #define IC_PRP_VF_RSC 0x90 57 #define IC_PP_RSC 0x94 58 #define IC_CMBP_1 0x98 59 #define IC_CMBP_2 0x9C 60 #define PF_CONF 0xA0 61 #define IDMAC_CONF 0xA4 62 #define IDMAC_CHA_EN 0xA8 63 #define IDMAC_CHA_PRI 0xAC 64 #define IDMAC_CHA_BUSY 0xB0 65 66 /* Image Converter Register bits */ 67 #define IC_CONF_PRPENC_EN 0x00000001 68 #define IC_CONF_PRPENC_CSC1 0x00000002 69 #define IC_CONF_PRPENC_ROT_EN 0x00000004 70 #define IC_CONF_PRPVF_EN 0x00000100 71 #define IC_CONF_PRPVF_CSC1 0x00000200 72 #define IC_CONF_PRPVF_CSC2 0x00000400 73 #define IC_CONF_PRPVF_CMB 0x00000800 74 #define IC_CONF_PRPVF_ROT_EN 0x00001000 75 #define IC_CONF_PP_EN 0x00010000 76 #define IC_CONF_PP_CSC1 0x00020000 77 #define IC_CONF_PP_CSC2 0x00040000 78 #define IC_CONF_PP_CMB 0x00080000 79 #define IC_CONF_PP_ROT_EN 0x00100000 80 #define IC_CONF_IC_GLB_LOC_A 0x10000000 81 #define IC_CONF_KEY_COLOR_EN 0x20000000 82 #define IC_CONF_RWS_EN 0x40000000 83 #define IC_CONF_CSI_MEM_WR_EN 0x80000000 84 85 #define IDMA_CHAN_INVALID 0x000000FF 86 #define IDMA_IC_0 0x00000001 87 #define IDMA_IC_1 0x00000002 88 #define IDMA_IC_2 0x00000004 89 #define IDMA_IC_3 0x00000008 90 #define IDMA_IC_4 0x00000010 91 #define IDMA_IC_5 0x00000020 92 #define IDMA_IC_6 0x00000040 93 #define IDMA_IC_7 0x00000080 94 #define IDMA_IC_8 0x00000100 95 #define IDMA_IC_9 0x00000200 96 #define IDMA_IC_10 0x00000400 97 #define IDMA_IC_11 0x00000800 98 #define IDMA_IC_12 0x00001000 99 #define IDMA_IC_13 0x00002000 100 #define IDMA_SDC_BG 0x00004000 101 #define IDMA_SDC_FG 0x00008000 102 #define IDMA_SDC_MASK 0x00010000 103 #define IDMA_SDC_PARTIAL 0x00020000 104 #define IDMA_ADC_SYS1_WR 0x00040000 105 #define IDMA_ADC_SYS2_WR 0x00080000 106 #define IDMA_ADC_SYS1_CMD 0x00100000 107 #define IDMA_ADC_SYS2_CMD 0x00200000 108 #define IDMA_ADC_SYS1_RD 0x00400000 109 #define IDMA_ADC_SYS2_RD 0x00800000 110 #define IDMA_PF_QP 0x01000000 111 #define IDMA_PF_BSP 0x02000000 112 #define IDMA_PF_Y_IN 0x04000000 113 #define IDMA_PF_U_IN 0x08000000 114 #define IDMA_PF_V_IN 0x10000000 115 #define IDMA_PF_Y_OUT 0x20000000 116 #define IDMA_PF_U_OUT 0x40000000 117 #define IDMA_PF_V_OUT 0x80000000 118 119 #define TSTAT_PF_H264_PAUSE 0x00000001 120 #define TSTAT_CSI2MEM_MASK 0x0000000C 121 #define TSTAT_CSI2MEM_OFFSET 2 122 #define TSTAT_VF_MASK 0x00000600 123 #define TSTAT_VF_OFFSET 9 124 #define TSTAT_VF_ROT_MASK 0x000C0000 125 #define TSTAT_VF_ROT_OFFSET 18 126 #define TSTAT_ENC_MASK 0x00000180 127 #define TSTAT_ENC_OFFSET 7 128 #define TSTAT_ENC_ROT_MASK 0x00030000 129 #define TSTAT_ENC_ROT_OFFSET 16 130 #define TSTAT_PP_MASK 0x00001800 131 #define TSTAT_PP_OFFSET 11 132 #define TSTAT_PP_ROT_MASK 0x00300000 133 #define TSTAT_PP_ROT_OFFSET 20 134 #define TSTAT_PF_MASK 0x00C00000 135 #define TSTAT_PF_OFFSET 22 136 #define TSTAT_ADCSYS1_MASK 0x03000000 137 #define TSTAT_ADCSYS1_OFFSET 24 138 #define TSTAT_ADCSYS2_MASK 0x0C000000 139 #define TSTAT_ADCSYS2_OFFSET 26 140 141 #define TASK_STAT_IDLE 0 142 #define TASK_STAT_ACTIVE 1 143 #define TASK_STAT_WAIT4READY 2 144 145 struct idmac { 146 struct dma_device dma; 147 }; 148 149 struct ipu { 150 void __iomem *reg_ipu; 151 void __iomem *reg_ic; 152 unsigned int irq_fn; /* IPU Function IRQ to the CPU */ 153 unsigned int irq_err; /* IPU Error IRQ to the CPU */ 154 unsigned int irq_base; /* Beginning of the IPU IRQ range */ 155 unsigned long channel_init_mask; 156 spinlock_t lock; 157 struct clk *ipu_clk; 158 struct device *dev; 159 struct idmac idmac; 160 struct idmac_channel channel[IPU_CHANNELS_NUM]; 161 struct tasklet_struct tasklet; 162 }; 163 164 #define to_idmac(d) container_of(d, struct idmac, dma) 165 166 extern int ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev); 167 extern void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev); 168 169 extern bool ipu_irq_status(uint32_t irq); 170 extern int ipu_irq_map(unsigned int source); 171 extern int ipu_irq_unmap(unsigned int source); 172 173 #endif 174