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Searched refs:IS_VALLEYVIEW (Results 1 – 25 of 46) sorted by relevance

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/drivers/gpu/drm/i915/display/
Dg4x_dp.c86 } else if (IS_VALLEYVIEW(dev_priv)) { in g4x_dp_set_clock()
486 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dp_link_down()
677 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_enable_dp()
687 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_enable_dp()
1290 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dp_encoder_reset()
1347 } else if (IS_VALLEYVIEW(dev_priv)) { in g4x_dp_init()
1368 else if (IS_VALLEYVIEW(dev_priv)) in g4x_dp_init()
1377 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || in g4x_dp_init()
Dintel_pps.c367 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_pps_get_registers()
409 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in edp_have_panel_power()
422 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in edp_have_panel_vdd()
1298 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in pps_init_registers()
1359 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_pps_encoder_reset()
1389 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_pps_unlock_regs_wa()
1406 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_pps_setup()
Dintel_dsi_vbt.c396 else if (IS_VALLEYVIEW(dev_priv)) in mipi_exec_gpio()
886 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_dsi_vbt_gpio_init()
892 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { in intel_dsi_vbt_gpio_init()
946 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_dsi_vbt_gpio_cleanup()
950 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { in intel_dsi_vbt_gpio_cleanup()
Dintel_pipe_crc.c417 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in get_new_crc_ctl_reg()
547 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_is_valid_crc_source()
623 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_crtc_set_crc_source()
Dintel_drrs.c168 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_dp_set_drrs_state()
173 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_dp_set_drrs_state()
Dintel_cdclk.c445 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) in vlv_calc_cdclk()
457 if (IS_VALLEYVIEW(dev_priv)) { in vlv_calc_voltage_level()
492 if (IS_VALLEYVIEW(dev_priv)) in vlv_get_cdclk()
2118 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_crtc_compute_min_cdclk()
2127 IS_VALLEYVIEW(dev_priv)) in intel_crtc_compute_min_cdclk()
2674 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_update_max_cdclk()
2706 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_update_cdclk()
2837 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_read_rawclk()
2915 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
2932 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_init_cdclk_hooks()
Dintel_vga.c17 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_vga_cntrl_reg()
Dintel_crtc.c303 IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv)) in intel_crtc_init()
398 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_pipe_update_start()
Dintel_crt.c356 else if (IS_VALLEYVIEW(dev_priv)) in intel_crt_mode_valid()
567 if (IS_VALLEYVIEW(dev_priv)) in intel_crt_detect_hotplug()
1004 else if (IS_VALLEYVIEW(dev_priv)) in intel_crt_init()
Di9xx_plane.c799 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_primary_plane_create()
833 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_primary_plane_create()
859 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_primary_plane_create()
Dintel_lpe_audio.c185 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in lpe_audio_detect()
Dintel_audio.c707 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in ilk_audio_codec_disable()
767 } else if (IS_VALLEYVIEW(dev_priv) || in ilk_audio_codec_enable()
927 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_init_audio_hooks()
/drivers/gpu/drm/i915/selftests/
Dintel_uncore.c159 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) { in live_forcewake_ops()
270 !IS_VALLEYVIEW(gt->i915) && in live_forcewake_domains()
/drivers/gpu/drm/i915/
Dvlv_suspend.c395 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in vlv_suspend_complete()
440 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in vlv_resume_prepare()
470 if (!IS_VALLEYVIEW(i915)) in vlv_suspend_init()
Di915_sysfs.c532 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in i915_setup_sysfs()
556 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i915_setup_sysfs()
574 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i915_teardown_sysfs()
Dintel_sideband.c62 if (IS_VALLEYVIEW(i915)) { in __vlv_punit_get()
70 if (IS_VALLEYVIEW(i915)) in __vlv_punit_put()
Di915_drv.c158 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_setup_mchbar()
1593 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in intel_runtime_suspend()
1639 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { in intel_runtime_resume()
Di915_irq.c187 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in intel_hpd_init_pins()
1562 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_ack()
1601 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_handler()
1616 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_hpd_irq_handler()
4370 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_irq_init()
4420 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_handler()
4445 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_reset()
4470 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_postinstall()
Dintel_device_info.c301 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_device_info_runtime_init()
/drivers/gpu/drm/i915/gt/
Dintel_rc6.c555 else if (IS_VALLEYVIEW(i915)) in intel_rc6_init()
593 else if (IS_VALLEYVIEW(i915)) in intel_rc6_enable()
758 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in intel_rc6_residency_ns()
Dintel_rps.c698 if (IS_VALLEYVIEW(gt->i915)) in rps_set_power()
831 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in rps_set()
1388 else if (IS_VALLEYVIEW(i915)) in intel_rps_enable()
1483 else if (IS_VALLEYVIEW(i915)) in intel_gpu_freq()
1500 else if (IS_VALLEYVIEW(i915)) in intel_freq_opcode()
1859 else if (IS_VALLEYVIEW(i915)) in intel_rps_init()
1925 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_rps_get_cagf()
1946 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in read_cagf()
Dselftest_rc6.c51 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in live_rc6_manual()
Dintel_ggtt_fencing.c572 if (GRAPHICS_VER(i915) >= 8 || IS_VALLEYVIEW(i915)) { in detect_bit_6_swizzle()
848 !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) in intel_ggtt_init_fences()
Ddebugfs_gt_pm.c231 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in drpc_show()
263 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in frequency_show()
Dgen7_renderclear.c401 ((IS_IVB_GT1(i915) || IS_VALLEYVIEW(i915)) ? in emit_batch()

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