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Searched refs:MCIF_WB_BUFMGR_SW_CONTROL (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_mmhubbub.c83 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, params->swlock); in mmhubbub2_config_mcif_buf()
141 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, 1); in mmhubbub2_config_mcif_buf()
213 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, params->sw_int_en); in mmhubbub2_config_mcif_irq()
214 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, params->sw_slice_int_en); in mmhubbub2_config_mcif_irq()
215 …REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, params->sw_overrun_int_en… in mmhubbub2_config_mcif_irq()
226 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, 1); in mmhubbub2_enable_mcif()
234 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, 0); in mmhubbub2_disable_mcif()
284 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0xf); in mcifwb2_dump_frame()
289 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0x0); in mcifwb2_dump_frame()
Ddcn20_mmhubbub.h40 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
422 uint32_t MCIF_WB_BUFMGR_SW_CONTROL;\
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_mmhubbub.h42 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
93 SRI2(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
279 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
280 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
281 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
282 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
283 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
284 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
285 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
Ddcn30_mmhubbub.c149 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, 1); in mmhubbub3_config_mcif_buf()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dwb.h58 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
221 uint32_t MCIF_WB_BUFMGR_SW_CONTROL; member