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Searched refs:MCIF_WB_BUFMGR_VCE_CONTROL (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_mmhubbub.h63 SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
114 SRI2(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
366 SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\
367 SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\
368 SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\
369 SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
370 SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\
371 SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
Ddcn30_mmhubbub.c206 REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1); in mmhubbub3_config_mcif_arb()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_mmhubbub.c199 REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1); in mmhubbub2_config_mcif_arb()
217 REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, params->vce_int_en); in mmhubbub2_config_mcif_irq()
218 REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, params->vce_slice_int_en); in mmhubbub2_config_mcif_irq()
Ddcn20_mmhubbub.h72 SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
454 uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;\
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dwb.h78 SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
241 uint32_t MCIF_WB_BUFMGR_VCE_CONTROL; member