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Searched refs:MCIF_WB_NB_PSTATE_CONTROL (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_mmhubbub.c179 REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x0); in mmhubbub2_config_mcif_arb()
183 REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x1); in mmhubbub2_config_mcif_arb()
187 REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x2); in mmhubbub2_config_mcif_arb()
191 REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x3); in mmhubbub2_config_mcif_arb()
Ddcn20_mmhubbub.h74 SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
456 uint32_t MCIF_WB_NB_PSTATE_CONTROL;\
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_mmhubbub.h65 SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
116 SRI2(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
374 SF(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
375 SF(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
376 SF(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dwb.h80 SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
243 uint32_t MCIF_WB_NB_PSTATE_CONTROL; member