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Searched refs:MC_SEQ_MISC0_GDDR5_SHIFT (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/radeon/
Dbtcd.h120 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 macro
Dnid.h210 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 macro
791 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 macro
Drv770d.h286 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 macro
Dsid.h558 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 macro
Dcikd.h683 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 macro
Dni.c658 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT; in ni_mc_load_microcode()
Drv770_dpm.c1598 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) == in rv770_get_memory_type()
Dsi_dpm.c3192 …ddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); in si_is_special_1gb_platform()
Dci_dpm.c5064 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) == in ci_get_memory_type()
/drivers/gpu/drm/amd/amdgpu/
Dsid.h559 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 macro
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu7_hwmgr.c80 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 macro
/drivers/gpu/drm/amd/pm/powerplay/
Dsi_dpm.c3650 …ddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); in si_is_special_1gb_platform()