Searched refs:MDP_SSPP_TOP0_INTR (Results 1 – 2 of 2) sorted by relevance
| /drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hw_catalog.c | 64 #define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
75 #define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
81 #define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
88 #define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
766 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
767 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
769 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
770 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
772 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
773 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
[all …]
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| D | dpu_hw_interrupts.h | 17 MDP_SSPP_TOP0_INTR, enumerator
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