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Searched refs:MIE (Results 1 – 14 of 14) sorted by relevance

/drivers/net/hamradio/
Dz8530.h110 #define MIE 8 /* Master Interrupt Enable */ macro
Ddmascc.c486 write_scc(priv, R9, FHWRES | MIE | NV); in setup_adapter()
750 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); in scc_open()
872 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); in scc_close()
Dscc.c882 or(scc,R9,MIE); /* master interrupt enable */ in init_channel()
/drivers/tty/serial/
Dzs.h164 #define MIE 8 /* Master Interrupt Enable */ macro
Dip22zilog.h146 #define MIE 8 /* Master Interrupt Enable */ macro
Dsunzilog.h147 #define MIE 8 /* Master Interrupt Enable */ macro
Dpmac_zilog.h239 #define MIE 8 /* Master Interrupt Enable */ macro
Dsunzilog.c1358 up->curregs[R9] |= MIE; in sunzilog_init_hw()
1384 up->curregs[R9] |= MIE; in sunzilog_init_hw()
1593 up->curregs[R9] |= MIE; in sunzilog_init()
1630 up->curregs[R9] &= ~MIE; in sunzilog_exit()
Dip22zilog.c1144 up->curregs[R9] = NV | MIE; in ip22zilog_prepare()
Dzs.c116 MIE | DLC | NV, /* write 9 */
Dpmac_zilog.c870 uap->curregs[R9] |= NV | MIE; in __pmz_startup()
/drivers/i2c/busses/
Di2c-rcar.c58 #define MIE (1 << 3) /* master if enable */ macro
92 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
93 #define RCAR_BUS_PHASE_DATA (MDBS | MIE)
94 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
/drivers/net/wan/
Dz85230.h131 #define MIE 8 /* Master Interrupt Enable */ macro
Dz85230.c213 9, NV | MIE | NORESET,
235 9, NV | MIE | NORESET,