1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers:
4 *
5 * device name digital output 7-bit I2C slave address (pin selectable)
6 * ---------------------------------------------------------------------
7 * MMA8451Q 14 bit 0x1c / 0x1d
8 * MMA8452Q 12 bit 0x1c / 0x1d
9 * MMA8453Q 10 bit 0x1c / 0x1d
10 * MMA8652FC 12 bit 0x1d
11 * MMA8653FC 10 bit 0x1d
12 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f
13 *
14 * Copyright 2015 Martin Kepplinger <martink@posteo.de>
15 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
16 *
17 *
18 * TODO: orientation events
19 */
20
21 #include <linux/module.h>
22 #include <linux/i2c.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/sysfs.h>
25 #include <linux/iio/buffer.h>
26 #include <linux/iio/trigger.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/triggered_buffer.h>
29 #include <linux/iio/events.h>
30 #include <linux/delay.h>
31 #include <linux/of_device.h>
32 #include <linux/of_irq.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/regulator/consumer.h>
35
36 #define MMA8452_STATUS 0x00
37 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
38 #define MMA8452_OUT_X 0x01 /* MSB first */
39 #define MMA8452_OUT_Y 0x03
40 #define MMA8452_OUT_Z 0x05
41 #define MMA8452_INT_SRC 0x0c
42 #define MMA8452_WHO_AM_I 0x0d
43 #define MMA8452_DATA_CFG 0x0e
44 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
45 #define MMA8452_DATA_CFG_FS_2G 0
46 #define MMA8452_DATA_CFG_FS_4G 1
47 #define MMA8452_DATA_CFG_FS_8G 2
48 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
49 #define MMA8452_HP_FILTER_CUTOFF 0x0f
50 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
51 #define MMA8452_FF_MT_CFG 0x15
52 #define MMA8452_FF_MT_CFG_OAE BIT(6)
53 #define MMA8452_FF_MT_CFG_ELE BIT(7)
54 #define MMA8452_FF_MT_SRC 0x16
55 #define MMA8452_FF_MT_SRC_XHE BIT(1)
56 #define MMA8452_FF_MT_SRC_YHE BIT(3)
57 #define MMA8452_FF_MT_SRC_ZHE BIT(5)
58 #define MMA8452_FF_MT_THS 0x17
59 #define MMA8452_FF_MT_THS_MASK 0x7f
60 #define MMA8452_FF_MT_COUNT 0x18
61 #define MMA8452_FF_MT_CHAN_SHIFT 3
62 #define MMA8452_TRANSIENT_CFG 0x1d
63 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
64 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
65 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
66 #define MMA8452_TRANSIENT_SRC 0x1e
67 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
68 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
69 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
70 #define MMA8452_TRANSIENT_THS 0x1f
71 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
72 #define MMA8452_TRANSIENT_COUNT 0x20
73 #define MMA8452_TRANSIENT_CHAN_SHIFT 1
74 #define MMA8452_CTRL_REG1 0x2a
75 #define MMA8452_CTRL_ACTIVE BIT(0)
76 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
77 #define MMA8452_CTRL_DR_SHIFT 3
78 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
79 #define MMA8452_CTRL_REG2 0x2b
80 #define MMA8452_CTRL_REG2_RST BIT(6)
81 #define MMA8452_CTRL_REG2_MODS_SHIFT 3
82 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b
83 #define MMA8452_CTRL_REG4 0x2d
84 #define MMA8452_CTRL_REG5 0x2e
85 #define MMA8452_OFF_X 0x2f
86 #define MMA8452_OFF_Y 0x30
87 #define MMA8452_OFF_Z 0x31
88
89 #define MMA8452_MAX_REG 0x31
90
91 #define MMA8452_INT_DRDY BIT(0)
92 #define MMA8452_INT_FF_MT BIT(2)
93 #define MMA8452_INT_TRANS BIT(5)
94
95 #define MMA8451_DEVICE_ID 0x1a
96 #define MMA8452_DEVICE_ID 0x2a
97 #define MMA8453_DEVICE_ID 0x3a
98 #define MMA8652_DEVICE_ID 0x4a
99 #define MMA8653_DEVICE_ID 0x5a
100 #define FXLS8471_DEVICE_ID 0x6a
101
102 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000
103
104 struct mma8452_data {
105 struct i2c_client *client;
106 struct mutex lock;
107 u8 ctrl_reg1;
108 u8 data_cfg;
109 const struct mma_chip_info *chip_info;
110 int sleep_val;
111 struct regulator *vdd_reg;
112 struct regulator *vddio_reg;
113
114 /* Ensure correct alignment of time stamp when present */
115 struct {
116 __be16 channels[3];
117 s64 ts __aligned(8);
118 } buffer;
119 };
120
121 /**
122 * struct mma8452_event_regs - chip specific data related to events
123 * @ev_cfg: event config register address
124 * @ev_cfg_ele: latch bit in event config register
125 * @ev_cfg_chan_shift: number of the bit to enable events in X
126 * direction; in event config register
127 * @ev_src: event source register address
128 * @ev_ths: event threshold register address
129 * @ev_ths_mask: mask for the threshold value
130 * @ev_count: event count (period) register address
131 *
132 * Since not all chips supported by the driver support comparing high pass
133 * filtered data for events (interrupts), different interrupt sources are
134 * used for different chips and the relevant registers are included here.
135 */
136 struct mma8452_event_regs {
137 u8 ev_cfg;
138 u8 ev_cfg_ele;
139 u8 ev_cfg_chan_shift;
140 u8 ev_src;
141 u8 ev_ths;
142 u8 ev_ths_mask;
143 u8 ev_count;
144 };
145
146 static const struct mma8452_event_regs ff_mt_ev_regs = {
147 .ev_cfg = MMA8452_FF_MT_CFG,
148 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
149 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT,
150 .ev_src = MMA8452_FF_MT_SRC,
151 .ev_ths = MMA8452_FF_MT_THS,
152 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
153 .ev_count = MMA8452_FF_MT_COUNT
154 };
155
156 static const struct mma8452_event_regs trans_ev_regs = {
157 .ev_cfg = MMA8452_TRANSIENT_CFG,
158 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
159 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT,
160 .ev_src = MMA8452_TRANSIENT_SRC,
161 .ev_ths = MMA8452_TRANSIENT_THS,
162 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
163 .ev_count = MMA8452_TRANSIENT_COUNT,
164 };
165
166 /**
167 * struct mma_chip_info - chip specific data
168 * @chip_id: WHO_AM_I register's value
169 * @channels: struct iio_chan_spec matching the device's
170 * capabilities
171 * @num_channels: number of channels
172 * @mma_scales: scale factors for converting register values
173 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
174 * per mode: m/s^2 and micro m/s^2
175 * @all_events: all events supported by this chip
176 * @enabled_events: event flags enabled and handled by this driver
177 */
178 struct mma_chip_info {
179 const char *name;
180 u8 chip_id;
181 const struct iio_chan_spec *channels;
182 int num_channels;
183 const int mma_scales[3][2];
184 int all_events;
185 int enabled_events;
186 };
187
188 enum {
189 idx_x,
190 idx_y,
191 idx_z,
192 idx_ts,
193 };
194
mma8452_drdy(struct mma8452_data * data)195 static int mma8452_drdy(struct mma8452_data *data)
196 {
197 int tries = 150;
198
199 while (tries-- > 0) {
200 int ret = i2c_smbus_read_byte_data(data->client,
201 MMA8452_STATUS);
202 if (ret < 0)
203 return ret;
204 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
205 return 0;
206
207 if (data->sleep_val <= 20)
208 usleep_range(data->sleep_val * 250,
209 data->sleep_val * 500);
210 else
211 msleep(20);
212 }
213
214 dev_err(&data->client->dev, "data not ready\n");
215
216 return -EIO;
217 }
218
mma8452_set_runtime_pm_state(struct i2c_client * client,bool on)219 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
220 {
221 #ifdef CONFIG_PM
222 int ret;
223
224 if (on) {
225 ret = pm_runtime_resume_and_get(&client->dev);
226 } else {
227 pm_runtime_mark_last_busy(&client->dev);
228 ret = pm_runtime_put_autosuspend(&client->dev);
229 }
230
231 if (ret < 0) {
232 dev_err(&client->dev,
233 "failed to change power state to %d\n", on);
234
235 return ret;
236 }
237 #endif
238
239 return 0;
240 }
241
mma8452_read(struct mma8452_data * data,__be16 buf[3])242 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
243 {
244 int ret = mma8452_drdy(data);
245
246 if (ret < 0)
247 return ret;
248
249 ret = mma8452_set_runtime_pm_state(data->client, true);
250 if (ret)
251 return ret;
252
253 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
254 3 * sizeof(__be16), (u8 *)buf);
255
256 ret = mma8452_set_runtime_pm_state(data->client, false);
257
258 return ret;
259 }
260
mma8452_show_int_plus_micros(char * buf,const int (* vals)[2],int n)261 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
262 int n)
263 {
264 size_t len = 0;
265
266 while (n-- > 0)
267 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
268 vals[n][0], vals[n][1]);
269
270 /* replace trailing space by newline */
271 buf[len - 1] = '\n';
272
273 return len;
274 }
275
mma8452_get_int_plus_micros_index(const int (* vals)[2],int n,int val,int val2)276 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
277 int val, int val2)
278 {
279 while (n-- > 0)
280 if (val == vals[n][0] && val2 == vals[n][1])
281 return n;
282
283 return -EINVAL;
284 }
285
mma8452_get_odr_index(struct mma8452_data * data)286 static unsigned int mma8452_get_odr_index(struct mma8452_data *data)
287 {
288 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
289 MMA8452_CTRL_DR_SHIFT;
290 }
291
292 static const int mma8452_samp_freq[8][2] = {
293 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
294 {6, 250000}, {1, 560000}
295 };
296
297 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */
298 static const unsigned int mma8452_time_step_us[4][8] = {
299 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */
300 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */
301 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/
302 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */
303 };
304
305 /* Datasheet table "High-Pass Filter Cutoff Options" */
306 static const int mma8452_hp_filter_cutoff[4][8][4][2] = {
307 { /* normal */
308 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
309 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
310 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
311 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
312 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
313 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
314 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
315 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
316 },
317 { /* low noise low power */
318 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
319 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
320 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
321 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
322 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
323 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
324 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
325 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
326 },
327 { /* high resolution */
328 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
329 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
330 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
331 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
332 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
333 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
334 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
335 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }
336 },
337 { /* low power */
338 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
339 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
340 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
341 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
342 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
343 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
344 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
345 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
346 }
347 };
348
349 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */
350 static const u16 mma8452_os_ratio[4][8] = {
351 /* 800 Hz, 400 Hz, ... , 1.56 Hz */
352 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */
353 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */
354 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */
355 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */
356 };
357
mma8452_get_power_mode(struct mma8452_data * data)358 static int mma8452_get_power_mode(struct mma8452_data *data)
359 {
360 int reg;
361
362 reg = i2c_smbus_read_byte_data(data->client,
363 MMA8452_CTRL_REG2);
364 if (reg < 0)
365 return reg;
366
367 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >>
368 MMA8452_CTRL_REG2_MODS_SHIFT);
369 }
370
mma8452_show_samp_freq_avail(struct device * dev,struct device_attribute * attr,char * buf)371 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
372 struct device_attribute *attr,
373 char *buf)
374 {
375 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
376 ARRAY_SIZE(mma8452_samp_freq));
377 }
378
mma8452_show_scale_avail(struct device * dev,struct device_attribute * attr,char * buf)379 static ssize_t mma8452_show_scale_avail(struct device *dev,
380 struct device_attribute *attr,
381 char *buf)
382 {
383 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
384 struct mma8452_data *data = iio_priv(indio_dev);
385
386 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
387 ARRAY_SIZE(data->chip_info->mma_scales));
388 }
389
mma8452_show_hp_cutoff_avail(struct device * dev,struct device_attribute * attr,char * buf)390 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
391 struct device_attribute *attr,
392 char *buf)
393 {
394 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
395 struct mma8452_data *data = iio_priv(indio_dev);
396 int i, j;
397
398 i = mma8452_get_odr_index(data);
399 j = mma8452_get_power_mode(data);
400 if (j < 0)
401 return j;
402
403 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i],
404 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]));
405 }
406
mma8452_show_os_ratio_avail(struct device * dev,struct device_attribute * attr,char * buf)407 static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
408 struct device_attribute *attr,
409 char *buf)
410 {
411 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
412 struct mma8452_data *data = iio_priv(indio_dev);
413 int i = mma8452_get_odr_index(data);
414 int j;
415 u16 val = 0;
416 size_t len = 0;
417
418 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) {
419 if (val == mma8452_os_ratio[j][i])
420 continue;
421
422 val = mma8452_os_ratio[j][i];
423
424 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val);
425 }
426 buf[len - 1] = '\n';
427
428 return len;
429 }
430
431 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
432 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444,
433 mma8452_show_scale_avail, NULL, 0);
434 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
435 0444, mma8452_show_hp_cutoff_avail, NULL, 0);
436 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444,
437 mma8452_show_os_ratio_avail, NULL, 0);
438
mma8452_get_samp_freq_index(struct mma8452_data * data,int val,int val2)439 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
440 int val, int val2)
441 {
442 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
443 ARRAY_SIZE(mma8452_samp_freq),
444 val, val2);
445 }
446
mma8452_get_scale_index(struct mma8452_data * data,int val,int val2)447 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
448 {
449 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
450 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
451 }
452
mma8452_get_hp_filter_index(struct mma8452_data * data,int val,int val2)453 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
454 int val, int val2)
455 {
456 int i, j;
457
458 i = mma8452_get_odr_index(data);
459 j = mma8452_get_power_mode(data);
460 if (j < 0)
461 return j;
462
463 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i],
464 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2);
465 }
466
mma8452_read_hp_filter(struct mma8452_data * data,int * hz,int * uHz)467 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
468 {
469 int j, i, ret;
470
471 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
472 if (ret < 0)
473 return ret;
474
475 i = mma8452_get_odr_index(data);
476 j = mma8452_get_power_mode(data);
477 if (j < 0)
478 return j;
479
480 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
481 *hz = mma8452_hp_filter_cutoff[j][i][ret][0];
482 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1];
483
484 return 0;
485 }
486
mma8452_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)487 static int mma8452_read_raw(struct iio_dev *indio_dev,
488 struct iio_chan_spec const *chan,
489 int *val, int *val2, long mask)
490 {
491 struct mma8452_data *data = iio_priv(indio_dev);
492 __be16 buffer[3];
493 int i, ret;
494
495 switch (mask) {
496 case IIO_CHAN_INFO_RAW:
497 ret = iio_device_claim_direct_mode(indio_dev);
498 if (ret)
499 return ret;
500
501 mutex_lock(&data->lock);
502 ret = mma8452_read(data, buffer);
503 mutex_unlock(&data->lock);
504 iio_device_release_direct_mode(indio_dev);
505 if (ret < 0)
506 return ret;
507
508 *val = sign_extend32(be16_to_cpu(
509 buffer[chan->scan_index]) >> chan->scan_type.shift,
510 chan->scan_type.realbits - 1);
511
512 return IIO_VAL_INT;
513 case IIO_CHAN_INFO_SCALE:
514 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
515 *val = data->chip_info->mma_scales[i][0];
516 *val2 = data->chip_info->mma_scales[i][1];
517
518 return IIO_VAL_INT_PLUS_MICRO;
519 case IIO_CHAN_INFO_SAMP_FREQ:
520 i = mma8452_get_odr_index(data);
521 *val = mma8452_samp_freq[i][0];
522 *val2 = mma8452_samp_freq[i][1];
523
524 return IIO_VAL_INT_PLUS_MICRO;
525 case IIO_CHAN_INFO_CALIBBIAS:
526 ret = i2c_smbus_read_byte_data(data->client,
527 MMA8452_OFF_X +
528 chan->scan_index);
529 if (ret < 0)
530 return ret;
531
532 *val = sign_extend32(ret, 7);
533
534 return IIO_VAL_INT;
535 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
536 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
537 ret = mma8452_read_hp_filter(data, val, val2);
538 if (ret < 0)
539 return ret;
540 } else {
541 *val = 0;
542 *val2 = 0;
543 }
544
545 return IIO_VAL_INT_PLUS_MICRO;
546 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
547 ret = mma8452_get_power_mode(data);
548 if (ret < 0)
549 return ret;
550
551 i = mma8452_get_odr_index(data);
552
553 *val = mma8452_os_ratio[ret][i];
554 return IIO_VAL_INT;
555 }
556
557 return -EINVAL;
558 }
559
mma8452_calculate_sleep(struct mma8452_data * data)560 static int mma8452_calculate_sleep(struct mma8452_data *data)
561 {
562 int ret, i = mma8452_get_odr_index(data);
563
564 if (mma8452_samp_freq[i][0] > 0)
565 ret = 1000 / mma8452_samp_freq[i][0];
566 else
567 ret = 1000;
568
569 return ret == 0 ? 1 : ret;
570 }
571
mma8452_standby(struct mma8452_data * data)572 static int mma8452_standby(struct mma8452_data *data)
573 {
574 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
575 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
576 }
577
mma8452_active(struct mma8452_data * data)578 static int mma8452_active(struct mma8452_data *data)
579 {
580 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
581 data->ctrl_reg1);
582 }
583
584 /* returns >0 if active, 0 if in standby and <0 on error */
mma8452_is_active(struct mma8452_data * data)585 static int mma8452_is_active(struct mma8452_data *data)
586 {
587 int reg;
588
589 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
590 if (reg < 0)
591 return reg;
592
593 return reg & MMA8452_CTRL_ACTIVE;
594 }
595
mma8452_change_config(struct mma8452_data * data,u8 reg,u8 val)596 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
597 {
598 int ret;
599 int is_active;
600
601 mutex_lock(&data->lock);
602
603 is_active = mma8452_is_active(data);
604 if (is_active < 0) {
605 ret = is_active;
606 goto fail;
607 }
608
609 /* config can only be changed when in standby */
610 if (is_active > 0) {
611 ret = mma8452_standby(data);
612 if (ret < 0)
613 goto fail;
614 }
615
616 ret = i2c_smbus_write_byte_data(data->client, reg, val);
617 if (ret < 0)
618 goto fail;
619
620 if (is_active > 0) {
621 ret = mma8452_active(data);
622 if (ret < 0)
623 goto fail;
624 }
625
626 ret = 0;
627 fail:
628 mutex_unlock(&data->lock);
629
630 return ret;
631 }
632
mma8452_set_power_mode(struct mma8452_data * data,u8 mode)633 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
634 {
635 int reg;
636
637 reg = i2c_smbus_read_byte_data(data->client,
638 MMA8452_CTRL_REG2);
639 if (reg < 0)
640 return reg;
641
642 reg &= ~MMA8452_CTRL_REG2_MODS_MASK;
643 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT;
644
645 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg);
646 }
647
648 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
mma8452_freefall_mode_enabled(struct mma8452_data * data)649 static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
650 {
651 int val;
652
653 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
654 if (val < 0)
655 return val;
656
657 return !(val & MMA8452_FF_MT_CFG_OAE);
658 }
659
mma8452_set_freefall_mode(struct mma8452_data * data,bool state)660 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
661 {
662 int val;
663
664 if ((state && mma8452_freefall_mode_enabled(data)) ||
665 (!state && !(mma8452_freefall_mode_enabled(data))))
666 return 0;
667
668 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
669 if (val < 0)
670 return val;
671
672 if (state) {
673 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
674 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
675 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
676 val &= ~MMA8452_FF_MT_CFG_OAE;
677 } else {
678 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
679 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
680 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
681 val |= MMA8452_FF_MT_CFG_OAE;
682 }
683
684 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val);
685 }
686
mma8452_set_hp_filter_frequency(struct mma8452_data * data,int val,int val2)687 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
688 int val, int val2)
689 {
690 int i, reg;
691
692 i = mma8452_get_hp_filter_index(data, val, val2);
693 if (i < 0)
694 return i;
695
696 reg = i2c_smbus_read_byte_data(data->client,
697 MMA8452_HP_FILTER_CUTOFF);
698 if (reg < 0)
699 return reg;
700
701 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
702 reg |= i;
703
704 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
705 }
706
mma8452_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)707 static int mma8452_write_raw(struct iio_dev *indio_dev,
708 struct iio_chan_spec const *chan,
709 int val, int val2, long mask)
710 {
711 struct mma8452_data *data = iio_priv(indio_dev);
712 int i, ret;
713
714 ret = iio_device_claim_direct_mode(indio_dev);
715 if (ret)
716 return ret;
717
718 switch (mask) {
719 case IIO_CHAN_INFO_SAMP_FREQ:
720 i = mma8452_get_samp_freq_index(data, val, val2);
721 if (i < 0) {
722 ret = i;
723 break;
724 }
725 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
726 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
727
728 data->sleep_val = mma8452_calculate_sleep(data);
729
730 ret = mma8452_change_config(data, MMA8452_CTRL_REG1,
731 data->ctrl_reg1);
732 break;
733 case IIO_CHAN_INFO_SCALE:
734 i = mma8452_get_scale_index(data, val, val2);
735 if (i < 0) {
736 ret = i;
737 break;
738 }
739
740 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
741 data->data_cfg |= i;
742
743 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
744 data->data_cfg);
745 break;
746 case IIO_CHAN_INFO_CALIBBIAS:
747 if (val < -128 || val > 127) {
748 ret = -EINVAL;
749 break;
750 }
751
752 ret = mma8452_change_config(data,
753 MMA8452_OFF_X + chan->scan_index,
754 val);
755 break;
756
757 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
758 if (val == 0 && val2 == 0) {
759 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
760 } else {
761 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
762 ret = mma8452_set_hp_filter_frequency(data, val, val2);
763 if (ret < 0)
764 break;
765 }
766
767 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
768 data->data_cfg);
769 break;
770
771 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
772 ret = mma8452_get_odr_index(data);
773
774 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) {
775 if (mma8452_os_ratio[i][ret] == val) {
776 ret = mma8452_set_power_mode(data, i);
777 break;
778 }
779 }
780 break;
781 default:
782 ret = -EINVAL;
783 break;
784 }
785
786 iio_device_release_direct_mode(indio_dev);
787 return ret;
788 }
789
mma8452_get_event_regs(struct mma8452_data * data,const struct iio_chan_spec * chan,enum iio_event_direction dir,const struct mma8452_event_regs ** ev_reg)790 static int mma8452_get_event_regs(struct mma8452_data *data,
791 const struct iio_chan_spec *chan, enum iio_event_direction dir,
792 const struct mma8452_event_regs **ev_reg)
793 {
794 if (!chan)
795 return -EINVAL;
796
797 switch (chan->type) {
798 case IIO_ACCEL:
799 switch (dir) {
800 case IIO_EV_DIR_RISING:
801 if ((data->chip_info->all_events
802 & MMA8452_INT_TRANS) &&
803 (data->chip_info->enabled_events
804 & MMA8452_INT_TRANS))
805 *ev_reg = &trans_ev_regs;
806 else
807 *ev_reg = &ff_mt_ev_regs;
808 return 0;
809 case IIO_EV_DIR_FALLING:
810 *ev_reg = &ff_mt_ev_regs;
811 return 0;
812 default:
813 return -EINVAL;
814 }
815 default:
816 return -EINVAL;
817 }
818 }
819
mma8452_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)820 static int mma8452_read_event_value(struct iio_dev *indio_dev,
821 const struct iio_chan_spec *chan,
822 enum iio_event_type type,
823 enum iio_event_direction dir,
824 enum iio_event_info info,
825 int *val, int *val2)
826 {
827 struct mma8452_data *data = iio_priv(indio_dev);
828 int ret, us, power_mode;
829 const struct mma8452_event_regs *ev_regs;
830
831 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
832 if (ret)
833 return ret;
834
835 switch (info) {
836 case IIO_EV_INFO_VALUE:
837 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths);
838 if (ret < 0)
839 return ret;
840
841 *val = ret & ev_regs->ev_ths_mask;
842
843 return IIO_VAL_INT;
844
845 case IIO_EV_INFO_PERIOD:
846 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count);
847 if (ret < 0)
848 return ret;
849
850 power_mode = mma8452_get_power_mode(data);
851 if (power_mode < 0)
852 return power_mode;
853
854 us = ret * mma8452_time_step_us[power_mode][
855 mma8452_get_odr_index(data)];
856 *val = us / USEC_PER_SEC;
857 *val2 = us % USEC_PER_SEC;
858
859 return IIO_VAL_INT_PLUS_MICRO;
860
861 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
862 ret = i2c_smbus_read_byte_data(data->client,
863 MMA8452_TRANSIENT_CFG);
864 if (ret < 0)
865 return ret;
866
867 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
868 *val = 0;
869 *val2 = 0;
870 } else {
871 ret = mma8452_read_hp_filter(data, val, val2);
872 if (ret < 0)
873 return ret;
874 }
875
876 return IIO_VAL_INT_PLUS_MICRO;
877
878 default:
879 return -EINVAL;
880 }
881 }
882
mma8452_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)883 static int mma8452_write_event_value(struct iio_dev *indio_dev,
884 const struct iio_chan_spec *chan,
885 enum iio_event_type type,
886 enum iio_event_direction dir,
887 enum iio_event_info info,
888 int val, int val2)
889 {
890 struct mma8452_data *data = iio_priv(indio_dev);
891 int ret, reg, steps;
892 const struct mma8452_event_regs *ev_regs;
893
894 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
895 if (ret)
896 return ret;
897
898 switch (info) {
899 case IIO_EV_INFO_VALUE:
900 if (val < 0 || val > ev_regs->ev_ths_mask)
901 return -EINVAL;
902
903 return mma8452_change_config(data, ev_regs->ev_ths, val);
904
905 case IIO_EV_INFO_PERIOD:
906 ret = mma8452_get_power_mode(data);
907 if (ret < 0)
908 return ret;
909
910 steps = (val * USEC_PER_SEC + val2) /
911 mma8452_time_step_us[ret][
912 mma8452_get_odr_index(data)];
913
914 if (steps < 0 || steps > 0xff)
915 return -EINVAL;
916
917 return mma8452_change_config(data, ev_regs->ev_count, steps);
918
919 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
920 reg = i2c_smbus_read_byte_data(data->client,
921 MMA8452_TRANSIENT_CFG);
922 if (reg < 0)
923 return reg;
924
925 if (val == 0 && val2 == 0) {
926 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
927 } else {
928 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
929 ret = mma8452_set_hp_filter_frequency(data, val, val2);
930 if (ret < 0)
931 return ret;
932 }
933
934 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
935
936 default:
937 return -EINVAL;
938 }
939 }
940
mma8452_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)941 static int mma8452_read_event_config(struct iio_dev *indio_dev,
942 const struct iio_chan_spec *chan,
943 enum iio_event_type type,
944 enum iio_event_direction dir)
945 {
946 struct mma8452_data *data = iio_priv(indio_dev);
947 int ret;
948 const struct mma8452_event_regs *ev_regs;
949
950 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
951 if (ret)
952 return ret;
953
954 switch (dir) {
955 case IIO_EV_DIR_FALLING:
956 return mma8452_freefall_mode_enabled(data);
957 case IIO_EV_DIR_RISING:
958 ret = i2c_smbus_read_byte_data(data->client,
959 ev_regs->ev_cfg);
960 if (ret < 0)
961 return ret;
962
963 return !!(ret & BIT(chan->scan_index +
964 ev_regs->ev_cfg_chan_shift));
965 default:
966 return -EINVAL;
967 }
968 }
969
mma8452_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)970 static int mma8452_write_event_config(struct iio_dev *indio_dev,
971 const struct iio_chan_spec *chan,
972 enum iio_event_type type,
973 enum iio_event_direction dir,
974 int state)
975 {
976 struct mma8452_data *data = iio_priv(indio_dev);
977 int val, ret;
978 const struct mma8452_event_regs *ev_regs;
979
980 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
981 if (ret)
982 return ret;
983
984 ret = mma8452_set_runtime_pm_state(data->client, state);
985 if (ret)
986 return ret;
987
988 switch (dir) {
989 case IIO_EV_DIR_FALLING:
990 return mma8452_set_freefall_mode(data, state);
991 case IIO_EV_DIR_RISING:
992 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg);
993 if (val < 0)
994 return val;
995
996 if (state) {
997 if (mma8452_freefall_mode_enabled(data)) {
998 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift);
999 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift);
1000 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift);
1001 val |= MMA8452_FF_MT_CFG_OAE;
1002 }
1003 val |= BIT(chan->scan_index +
1004 ev_regs->ev_cfg_chan_shift);
1005 } else {
1006 if (mma8452_freefall_mode_enabled(data))
1007 return 0;
1008
1009 val &= ~BIT(chan->scan_index +
1010 ev_regs->ev_cfg_chan_shift);
1011 }
1012
1013 val |= ev_regs->ev_cfg_ele;
1014
1015 return mma8452_change_config(data, ev_regs->ev_cfg, val);
1016 default:
1017 return -EINVAL;
1018 }
1019 }
1020
mma8452_transient_interrupt(struct iio_dev * indio_dev)1021 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
1022 {
1023 struct mma8452_data *data = iio_priv(indio_dev);
1024 s64 ts = iio_get_time_ns(indio_dev);
1025 int src;
1026
1027 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
1028 if (src < 0)
1029 return;
1030
1031 if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
1032 iio_push_event(indio_dev,
1033 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
1034 IIO_EV_TYPE_MAG,
1035 IIO_EV_DIR_RISING),
1036 ts);
1037
1038 if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
1039 iio_push_event(indio_dev,
1040 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
1041 IIO_EV_TYPE_MAG,
1042 IIO_EV_DIR_RISING),
1043 ts);
1044
1045 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
1046 iio_push_event(indio_dev,
1047 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
1048 IIO_EV_TYPE_MAG,
1049 IIO_EV_DIR_RISING),
1050 ts);
1051 }
1052
mma8452_interrupt(int irq,void * p)1053 static irqreturn_t mma8452_interrupt(int irq, void *p)
1054 {
1055 struct iio_dev *indio_dev = p;
1056 struct mma8452_data *data = iio_priv(indio_dev);
1057 int ret = IRQ_NONE;
1058 int src;
1059
1060 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
1061 if (src < 0)
1062 return IRQ_NONE;
1063
1064 if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY)))
1065 return IRQ_NONE;
1066
1067 if (src & MMA8452_INT_DRDY) {
1068 iio_trigger_poll_chained(indio_dev->trig);
1069 ret = IRQ_HANDLED;
1070 }
1071
1072 if (src & MMA8452_INT_FF_MT) {
1073 if (mma8452_freefall_mode_enabled(data)) {
1074 s64 ts = iio_get_time_ns(indio_dev);
1075
1076 iio_push_event(indio_dev,
1077 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1078 IIO_MOD_X_AND_Y_AND_Z,
1079 IIO_EV_TYPE_MAG,
1080 IIO_EV_DIR_FALLING),
1081 ts);
1082 }
1083 ret = IRQ_HANDLED;
1084 }
1085
1086 if (src & MMA8452_INT_TRANS) {
1087 mma8452_transient_interrupt(indio_dev);
1088 ret = IRQ_HANDLED;
1089 }
1090
1091 return ret;
1092 }
1093
mma8452_trigger_handler(int irq,void * p)1094 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
1095 {
1096 struct iio_poll_func *pf = p;
1097 struct iio_dev *indio_dev = pf->indio_dev;
1098 struct mma8452_data *data = iio_priv(indio_dev);
1099 int ret;
1100
1101 ret = mma8452_read(data, data->buffer.channels);
1102 if (ret < 0)
1103 goto done;
1104
1105 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
1106 iio_get_time_ns(indio_dev));
1107
1108 done:
1109 iio_trigger_notify_done(indio_dev->trig);
1110
1111 return IRQ_HANDLED;
1112 }
1113
mma8452_reg_access_dbg(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)1114 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
1115 unsigned int reg, unsigned int writeval,
1116 unsigned int *readval)
1117 {
1118 int ret;
1119 struct mma8452_data *data = iio_priv(indio_dev);
1120
1121 if (reg > MMA8452_MAX_REG)
1122 return -EINVAL;
1123
1124 if (!readval)
1125 return mma8452_change_config(data, reg, writeval);
1126
1127 ret = i2c_smbus_read_byte_data(data->client, reg);
1128 if (ret < 0)
1129 return ret;
1130
1131 *readval = ret;
1132
1133 return 0;
1134 }
1135
1136 static const struct iio_event_spec mma8452_freefall_event[] = {
1137 {
1138 .type = IIO_EV_TYPE_MAG,
1139 .dir = IIO_EV_DIR_FALLING,
1140 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1141 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1142 BIT(IIO_EV_INFO_PERIOD) |
1143 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1144 },
1145 };
1146
1147 static const struct iio_event_spec mma8652_freefall_event[] = {
1148 {
1149 .type = IIO_EV_TYPE_MAG,
1150 .dir = IIO_EV_DIR_FALLING,
1151 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1152 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1153 BIT(IIO_EV_INFO_PERIOD)
1154 },
1155 };
1156
1157 static const struct iio_event_spec mma8452_transient_event[] = {
1158 {
1159 .type = IIO_EV_TYPE_MAG,
1160 .dir = IIO_EV_DIR_RISING,
1161 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1162 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1163 BIT(IIO_EV_INFO_PERIOD) |
1164 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1165 },
1166 };
1167
1168 static const struct iio_event_spec mma8452_motion_event[] = {
1169 {
1170 .type = IIO_EV_TYPE_MAG,
1171 .dir = IIO_EV_DIR_RISING,
1172 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1173 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1174 BIT(IIO_EV_INFO_PERIOD)
1175 },
1176 };
1177
1178 /*
1179 * Threshold is configured in fixed 8G/127 steps regardless of
1180 * currently selected scale for measurement.
1181 */
1182 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
1183
1184 static struct attribute *mma8452_event_attributes[] = {
1185 &iio_const_attr_accel_transient_scale.dev_attr.attr,
1186 NULL,
1187 };
1188
1189 static const struct attribute_group mma8452_event_attribute_group = {
1190 .attrs = mma8452_event_attributes,
1191 };
1192
1193 #define MMA8452_FREEFALL_CHANNEL(modifier) { \
1194 .type = IIO_ACCEL, \
1195 .modified = 1, \
1196 .channel2 = modifier, \
1197 .scan_index = -1, \
1198 .event_spec = mma8452_freefall_event, \
1199 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
1200 }
1201
1202 #define MMA8652_FREEFALL_CHANNEL(modifier) { \
1203 .type = IIO_ACCEL, \
1204 .modified = 1, \
1205 .channel2 = modifier, \
1206 .scan_index = -1, \
1207 .event_spec = mma8652_freefall_event, \
1208 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
1209 }
1210
1211 #define MMA8452_CHANNEL(axis, idx, bits) { \
1212 .type = IIO_ACCEL, \
1213 .modified = 1, \
1214 .channel2 = IIO_MOD_##axis, \
1215 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1216 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1217 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1218 BIT(IIO_CHAN_INFO_SCALE) | \
1219 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
1220 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1221 .scan_index = idx, \
1222 .scan_type = { \
1223 .sign = 's', \
1224 .realbits = (bits), \
1225 .storagebits = 16, \
1226 .shift = 16 - (bits), \
1227 .endianness = IIO_BE, \
1228 }, \
1229 .event_spec = mma8452_transient_event, \
1230 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1231 }
1232
1233 #define MMA8652_CHANNEL(axis, idx, bits) { \
1234 .type = IIO_ACCEL, \
1235 .modified = 1, \
1236 .channel2 = IIO_MOD_##axis, \
1237 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1238 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1239 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1240 BIT(IIO_CHAN_INFO_SCALE) | \
1241 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1242 .scan_index = idx, \
1243 .scan_type = { \
1244 .sign = 's', \
1245 .realbits = (bits), \
1246 .storagebits = 16, \
1247 .shift = 16 - (bits), \
1248 .endianness = IIO_BE, \
1249 }, \
1250 .event_spec = mma8452_motion_event, \
1251 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1252 }
1253
1254 static const struct iio_chan_spec mma8451_channels[] = {
1255 MMA8452_CHANNEL(X, idx_x, 14),
1256 MMA8452_CHANNEL(Y, idx_y, 14),
1257 MMA8452_CHANNEL(Z, idx_z, 14),
1258 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1259 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1260 };
1261
1262 static const struct iio_chan_spec mma8452_channels[] = {
1263 MMA8452_CHANNEL(X, idx_x, 12),
1264 MMA8452_CHANNEL(Y, idx_y, 12),
1265 MMA8452_CHANNEL(Z, idx_z, 12),
1266 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1267 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1268 };
1269
1270 static const struct iio_chan_spec mma8453_channels[] = {
1271 MMA8452_CHANNEL(X, idx_x, 10),
1272 MMA8452_CHANNEL(Y, idx_y, 10),
1273 MMA8452_CHANNEL(Z, idx_z, 10),
1274 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1275 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1276 };
1277
1278 static const struct iio_chan_spec mma8652_channels[] = {
1279 MMA8652_CHANNEL(X, idx_x, 12),
1280 MMA8652_CHANNEL(Y, idx_y, 12),
1281 MMA8652_CHANNEL(Z, idx_z, 12),
1282 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1283 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1284 };
1285
1286 static const struct iio_chan_spec mma8653_channels[] = {
1287 MMA8652_CHANNEL(X, idx_x, 10),
1288 MMA8652_CHANNEL(Y, idx_y, 10),
1289 MMA8652_CHANNEL(Z, idx_z, 10),
1290 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1291 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1292 };
1293
1294 enum {
1295 mma8451,
1296 mma8452,
1297 mma8453,
1298 mma8652,
1299 mma8653,
1300 fxls8471,
1301 };
1302
1303 static const struct mma_chip_info mma_chip_info_table[] = {
1304 [mma8451] = {
1305 .name = "mma8451",
1306 .chip_id = MMA8451_DEVICE_ID,
1307 .channels = mma8451_channels,
1308 .num_channels = ARRAY_SIZE(mma8451_channels),
1309 /*
1310 * Hardware has fullscale of -2G, -4G, -8G corresponding to
1311 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1312 * bit.
1313 * The userspace interface uses m/s^2 and we declare micro units
1314 * So scale factor for 12 bit here is given by:
1315 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1316 */
1317 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1318 /*
1319 * Although we enable the interrupt sources once and for
1320 * all here the event detection itself is not enabled until
1321 * userspace asks for it by mma8452_write_event_config()
1322 */
1323 .all_events = MMA8452_INT_DRDY |
1324 MMA8452_INT_TRANS |
1325 MMA8452_INT_FF_MT,
1326 .enabled_events = MMA8452_INT_TRANS |
1327 MMA8452_INT_FF_MT,
1328 },
1329 [mma8452] = {
1330 .name = "mma8452",
1331 .chip_id = MMA8452_DEVICE_ID,
1332 .channels = mma8452_channels,
1333 .num_channels = ARRAY_SIZE(mma8452_channels),
1334 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1335 /*
1336 * Although we enable the interrupt sources once and for
1337 * all here the event detection itself is not enabled until
1338 * userspace asks for it by mma8452_write_event_config()
1339 */
1340 .all_events = MMA8452_INT_DRDY |
1341 MMA8452_INT_TRANS |
1342 MMA8452_INT_FF_MT,
1343 .enabled_events = MMA8452_INT_TRANS |
1344 MMA8452_INT_FF_MT,
1345 },
1346 [mma8453] = {
1347 .name = "mma8453",
1348 .chip_id = MMA8453_DEVICE_ID,
1349 .channels = mma8453_channels,
1350 .num_channels = ARRAY_SIZE(mma8453_channels),
1351 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1352 /*
1353 * Although we enable the interrupt sources once and for
1354 * all here the event detection itself is not enabled until
1355 * userspace asks for it by mma8452_write_event_config()
1356 */
1357 .all_events = MMA8452_INT_DRDY |
1358 MMA8452_INT_TRANS |
1359 MMA8452_INT_FF_MT,
1360 .enabled_events = MMA8452_INT_TRANS |
1361 MMA8452_INT_FF_MT,
1362 },
1363 [mma8652] = {
1364 .name = "mma8652",
1365 .chip_id = MMA8652_DEVICE_ID,
1366 .channels = mma8652_channels,
1367 .num_channels = ARRAY_SIZE(mma8652_channels),
1368 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1369 .all_events = MMA8452_INT_DRDY |
1370 MMA8452_INT_FF_MT,
1371 .enabled_events = MMA8452_INT_FF_MT,
1372 },
1373 [mma8653] = {
1374 .name = "mma8653",
1375 .chip_id = MMA8653_DEVICE_ID,
1376 .channels = mma8653_channels,
1377 .num_channels = ARRAY_SIZE(mma8653_channels),
1378 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1379 /*
1380 * Although we enable the interrupt sources once and for
1381 * all here the event detection itself is not enabled until
1382 * userspace asks for it by mma8452_write_event_config()
1383 */
1384 .all_events = MMA8452_INT_DRDY |
1385 MMA8452_INT_FF_MT,
1386 .enabled_events = MMA8452_INT_FF_MT,
1387 },
1388 [fxls8471] = {
1389 .name = "fxls8471",
1390 .chip_id = FXLS8471_DEVICE_ID,
1391 .channels = mma8451_channels,
1392 .num_channels = ARRAY_SIZE(mma8451_channels),
1393 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1394 /*
1395 * Although we enable the interrupt sources once and for
1396 * all here the event detection itself is not enabled until
1397 * userspace asks for it by mma8452_write_event_config()
1398 */
1399 .all_events = MMA8452_INT_DRDY |
1400 MMA8452_INT_TRANS |
1401 MMA8452_INT_FF_MT,
1402 .enabled_events = MMA8452_INT_TRANS |
1403 MMA8452_INT_FF_MT,
1404 },
1405 };
1406
1407 static struct attribute *mma8452_attributes[] = {
1408 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1409 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1410 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1411 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr,
1412 NULL
1413 };
1414
1415 static const struct attribute_group mma8452_group = {
1416 .attrs = mma8452_attributes,
1417 };
1418
1419 static const struct iio_info mma8452_info = {
1420 .attrs = &mma8452_group,
1421 .read_raw = &mma8452_read_raw,
1422 .write_raw = &mma8452_write_raw,
1423 .event_attrs = &mma8452_event_attribute_group,
1424 .read_event_value = &mma8452_read_event_value,
1425 .write_event_value = &mma8452_write_event_value,
1426 .read_event_config = &mma8452_read_event_config,
1427 .write_event_config = &mma8452_write_event_config,
1428 .debugfs_reg_access = &mma8452_reg_access_dbg,
1429 };
1430
1431 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1432
mma8452_data_rdy_trigger_set_state(struct iio_trigger * trig,bool state)1433 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1434 bool state)
1435 {
1436 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1437 struct mma8452_data *data = iio_priv(indio_dev);
1438 int reg, ret;
1439
1440 ret = mma8452_set_runtime_pm_state(data->client, state);
1441 if (ret)
1442 return ret;
1443
1444 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1445 if (reg < 0)
1446 return reg;
1447
1448 if (state)
1449 reg |= MMA8452_INT_DRDY;
1450 else
1451 reg &= ~MMA8452_INT_DRDY;
1452
1453 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1454 }
1455
1456 static const struct iio_trigger_ops mma8452_trigger_ops = {
1457 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1458 .validate_device = iio_trigger_validate_own_device,
1459 };
1460
mma8452_trigger_setup(struct iio_dev * indio_dev)1461 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1462 {
1463 struct mma8452_data *data = iio_priv(indio_dev);
1464 struct iio_trigger *trig;
1465 int ret;
1466
1467 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1468 indio_dev->name,
1469 iio_device_id(indio_dev));
1470 if (!trig)
1471 return -ENOMEM;
1472
1473 trig->ops = &mma8452_trigger_ops;
1474 iio_trigger_set_drvdata(trig, indio_dev);
1475
1476 ret = iio_trigger_register(trig);
1477 if (ret)
1478 return ret;
1479
1480 indio_dev->trig = iio_trigger_get(trig);
1481
1482 return 0;
1483 }
1484
mma8452_trigger_cleanup(struct iio_dev * indio_dev)1485 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1486 {
1487 if (indio_dev->trig)
1488 iio_trigger_unregister(indio_dev->trig);
1489 }
1490
mma8452_reset(struct i2c_client * client)1491 static int mma8452_reset(struct i2c_client *client)
1492 {
1493 int i;
1494 int ret;
1495
1496 /*
1497 * Find on fxls8471, after config reset bit, it reset immediately,
1498 * and will not give ACK, so here do not check the return value.
1499 * The following code will read the reset register, and check whether
1500 * this reset works.
1501 */
1502 i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1503 MMA8452_CTRL_REG2_RST);
1504
1505 for (i = 0; i < 10; i++) {
1506 usleep_range(100, 200);
1507 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1508 if (ret == -EIO)
1509 continue; /* I2C comm reset */
1510 if (ret < 0)
1511 return ret;
1512 if (!(ret & MMA8452_CTRL_REG2_RST))
1513 return 0;
1514 }
1515
1516 return -ETIMEDOUT;
1517 }
1518
1519 static const struct of_device_id mma8452_dt_ids[] = {
1520 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1521 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1522 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1523 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1524 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1525 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] },
1526 { }
1527 };
1528 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1529
mma8452_probe(struct i2c_client * client,const struct i2c_device_id * id)1530 static int mma8452_probe(struct i2c_client *client,
1531 const struct i2c_device_id *id)
1532 {
1533 struct mma8452_data *data;
1534 struct iio_dev *indio_dev;
1535 int ret;
1536
1537 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1538 if (!indio_dev)
1539 return -ENOMEM;
1540
1541 data = iio_priv(indio_dev);
1542 data->client = client;
1543 mutex_init(&data->lock);
1544
1545 data->chip_info = device_get_match_data(&client->dev);
1546 if (!data->chip_info) {
1547 if (id) {
1548 data->chip_info = &mma_chip_info_table[id->driver_data];
1549 } else {
1550 dev_err(&client->dev, "unknown device model\n");
1551 return -ENODEV;
1552 }
1553 }
1554
1555 data->vdd_reg = devm_regulator_get(&client->dev, "vdd");
1556 if (IS_ERR(data->vdd_reg))
1557 return dev_err_probe(&client->dev, PTR_ERR(data->vdd_reg),
1558 "failed to get VDD regulator!\n");
1559
1560 data->vddio_reg = devm_regulator_get(&client->dev, "vddio");
1561 if (IS_ERR(data->vddio_reg))
1562 return dev_err_probe(&client->dev, PTR_ERR(data->vddio_reg),
1563 "failed to get VDDIO regulator!\n");
1564
1565 ret = regulator_enable(data->vdd_reg);
1566 if (ret) {
1567 dev_err(&client->dev, "failed to enable VDD regulator!\n");
1568 return ret;
1569 }
1570
1571 ret = regulator_enable(data->vddio_reg);
1572 if (ret) {
1573 dev_err(&client->dev, "failed to enable VDDIO regulator!\n");
1574 goto disable_regulator_vdd;
1575 }
1576
1577 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1578 if (ret < 0)
1579 goto disable_regulators;
1580
1581 switch (ret) {
1582 case MMA8451_DEVICE_ID:
1583 case MMA8452_DEVICE_ID:
1584 case MMA8453_DEVICE_ID:
1585 case MMA8652_DEVICE_ID:
1586 case MMA8653_DEVICE_ID:
1587 case FXLS8471_DEVICE_ID:
1588 if (ret == data->chip_info->chip_id)
1589 break;
1590 fallthrough;
1591 default:
1592 ret = -ENODEV;
1593 goto disable_regulators;
1594 }
1595
1596 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1597 data->chip_info->name, data->chip_info->chip_id);
1598
1599 i2c_set_clientdata(client, indio_dev);
1600 indio_dev->info = &mma8452_info;
1601 indio_dev->name = data->chip_info->name;
1602 indio_dev->modes = INDIO_DIRECT_MODE;
1603 indio_dev->channels = data->chip_info->channels;
1604 indio_dev->num_channels = data->chip_info->num_channels;
1605 indio_dev->available_scan_masks = mma8452_scan_masks;
1606
1607 ret = mma8452_reset(client);
1608 if (ret < 0)
1609 goto disable_regulators;
1610
1611 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1612 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1613 data->data_cfg);
1614 if (ret < 0)
1615 goto disable_regulators;
1616
1617 /*
1618 * By default set transient threshold to max to avoid events if
1619 * enabling without configuring threshold.
1620 */
1621 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1622 MMA8452_TRANSIENT_THS_MASK);
1623 if (ret < 0)
1624 goto disable_regulators;
1625
1626 if (client->irq) {
1627 int irq2;
1628
1629 irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1630
1631 if (irq2 == client->irq) {
1632 dev_dbg(&client->dev, "using interrupt line INT2\n");
1633 } else {
1634 ret = i2c_smbus_write_byte_data(client,
1635 MMA8452_CTRL_REG5,
1636 data->chip_info->all_events);
1637 if (ret < 0)
1638 goto disable_regulators;
1639
1640 dev_dbg(&client->dev, "using interrupt line INT1\n");
1641 }
1642
1643 ret = i2c_smbus_write_byte_data(client,
1644 MMA8452_CTRL_REG4,
1645 data->chip_info->enabled_events);
1646 if (ret < 0)
1647 goto disable_regulators;
1648
1649 ret = mma8452_trigger_setup(indio_dev);
1650 if (ret < 0)
1651 goto disable_regulators;
1652 }
1653
1654 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1655 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1656
1657 data->sleep_val = mma8452_calculate_sleep(data);
1658
1659 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1660 data->ctrl_reg1);
1661 if (ret < 0)
1662 goto trigger_cleanup;
1663
1664 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1665 mma8452_trigger_handler, NULL);
1666 if (ret < 0)
1667 goto trigger_cleanup;
1668
1669 if (client->irq) {
1670 ret = devm_request_threaded_irq(&client->dev,
1671 client->irq,
1672 NULL, mma8452_interrupt,
1673 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1674 client->name, indio_dev);
1675 if (ret)
1676 goto buffer_cleanup;
1677 }
1678
1679 ret = pm_runtime_set_active(&client->dev);
1680 if (ret < 0)
1681 goto buffer_cleanup;
1682
1683 pm_runtime_enable(&client->dev);
1684 pm_runtime_set_autosuspend_delay(&client->dev,
1685 MMA8452_AUTO_SUSPEND_DELAY_MS);
1686 pm_runtime_use_autosuspend(&client->dev);
1687
1688 ret = iio_device_register(indio_dev);
1689 if (ret < 0)
1690 goto buffer_cleanup;
1691
1692 ret = mma8452_set_freefall_mode(data, false);
1693 if (ret < 0)
1694 goto unregister_device;
1695
1696 return 0;
1697
1698 unregister_device:
1699 iio_device_unregister(indio_dev);
1700
1701 buffer_cleanup:
1702 iio_triggered_buffer_cleanup(indio_dev);
1703
1704 trigger_cleanup:
1705 mma8452_trigger_cleanup(indio_dev);
1706
1707 disable_regulators:
1708 regulator_disable(data->vddio_reg);
1709
1710 disable_regulator_vdd:
1711 regulator_disable(data->vdd_reg);
1712
1713 return ret;
1714 }
1715
mma8452_remove(struct i2c_client * client)1716 static int mma8452_remove(struct i2c_client *client)
1717 {
1718 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1719 struct mma8452_data *data = iio_priv(indio_dev);
1720
1721 iio_device_unregister(indio_dev);
1722
1723 pm_runtime_disable(&client->dev);
1724 pm_runtime_set_suspended(&client->dev);
1725
1726 iio_triggered_buffer_cleanup(indio_dev);
1727 mma8452_trigger_cleanup(indio_dev);
1728 mma8452_standby(iio_priv(indio_dev));
1729
1730 regulator_disable(data->vddio_reg);
1731 regulator_disable(data->vdd_reg);
1732
1733 return 0;
1734 }
1735
1736 #ifdef CONFIG_PM
mma8452_runtime_suspend(struct device * dev)1737 static int mma8452_runtime_suspend(struct device *dev)
1738 {
1739 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1740 struct mma8452_data *data = iio_priv(indio_dev);
1741 int ret;
1742
1743 mutex_lock(&data->lock);
1744 ret = mma8452_standby(data);
1745 mutex_unlock(&data->lock);
1746 if (ret < 0) {
1747 dev_err(&data->client->dev, "powering off device failed\n");
1748 return -EAGAIN;
1749 }
1750
1751 ret = regulator_disable(data->vddio_reg);
1752 if (ret) {
1753 dev_err(dev, "failed to disable VDDIO regulator\n");
1754 return ret;
1755 }
1756
1757 ret = regulator_disable(data->vdd_reg);
1758 if (ret) {
1759 dev_err(dev, "failed to disable VDD regulator\n");
1760 return ret;
1761 }
1762
1763 return 0;
1764 }
1765
mma8452_runtime_resume(struct device * dev)1766 static int mma8452_runtime_resume(struct device *dev)
1767 {
1768 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1769 struct mma8452_data *data = iio_priv(indio_dev);
1770 int ret, sleep_val;
1771
1772 ret = regulator_enable(data->vdd_reg);
1773 if (ret) {
1774 dev_err(dev, "failed to enable VDD regulator\n");
1775 return ret;
1776 }
1777
1778 ret = regulator_enable(data->vddio_reg);
1779 if (ret) {
1780 dev_err(dev, "failed to enable VDDIO regulator\n");
1781 regulator_disable(data->vdd_reg);
1782 return ret;
1783 }
1784
1785 ret = mma8452_active(data);
1786 if (ret < 0)
1787 goto runtime_resume_failed;
1788
1789 ret = mma8452_get_odr_index(data);
1790 sleep_val = 1000 / mma8452_samp_freq[ret][0];
1791 if (sleep_val < 20)
1792 usleep_range(sleep_val * 1000, 20000);
1793 else
1794 msleep_interruptible(sleep_val);
1795
1796 return 0;
1797
1798 runtime_resume_failed:
1799 regulator_disable(data->vddio_reg);
1800 regulator_disable(data->vdd_reg);
1801
1802 return ret;
1803 }
1804 #endif
1805
1806 static const struct dev_pm_ops mma8452_pm_ops = {
1807 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1808 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1809 mma8452_runtime_resume, NULL)
1810 };
1811
1812 static const struct i2c_device_id mma8452_id[] = {
1813 { "mma8451", mma8451 },
1814 { "mma8452", mma8452 },
1815 { "mma8453", mma8453 },
1816 { "mma8652", mma8652 },
1817 { "mma8653", mma8653 },
1818 { "fxls8471", fxls8471 },
1819 { }
1820 };
1821 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1822
1823 static struct i2c_driver mma8452_driver = {
1824 .driver = {
1825 .name = "mma8452",
1826 .of_match_table = mma8452_dt_ids,
1827 .pm = &mma8452_pm_ops,
1828 },
1829 .probe = mma8452_probe,
1830 .remove = mma8452_remove,
1831 .id_table = mma8452_id,
1832 };
1833 module_i2c_driver(mma8452_driver);
1834
1835 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1836 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver");
1837 MODULE_LICENSE("GPL");
1838