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Searched refs:MP1_BASE__INST0_SEG1 (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/include/
Dcyan_skillfish_ip_offset.h462 #define MP1_BASE__INST0_SEG1 0 macro
Dnavi10_ip_offset.h520 #define MP1_BASE__INST0_SEG1 0 macro
Dnavi14_ip_offset.h700 #define MP1_BASE__INST0_SEG1 0x00DC0000 macro
Dnavi12_ip_offset.h700 #define MP1_BASE__INST0_SEG1 0x00E80000 macro
Ddimgrey_cavefish_ip_offset.h707 #define MP1_BASE__INST0_SEG1 0x00E80000 macro
Dvega20_ip_offset.h547 #define MP1_BASE__INST0_SEG1 0 macro
Dsienna_cichlid_ip_offset.h707 #define MP1_BASE__INST0_SEG1 0x00DC0000 macro
Dbeige_goby_ip_offset.h834 #define MP1_BASE__INST0_SEG1 0x00DC0000 macro
Drenoir_ip_offset.h950 #define MP1_BASE__INST0_SEG1 0x02400400 macro
Dvega10_ip_offset.h366 #define MP1_BASE__INST0_SEG1 0 macro
Dyellow_carp_offset.h877 #define MP1_BASE__INST0_SEG1 0x0243FC00 macro
Dvangogh_ip_offset.h957 #define MP1_BASE__INST0_SEG1 0x0243FC00 macro
Darct_ip_offset.h695 #define MP1_BASE__INST0_SEG1 0x00016200 macro
Daldebaran_ip_offset.h1004 #define MP1_BASE__INST0_SEG1 0x00DC0000 macro