| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | pllnv04.c | 151 int M1, N1, M2, N2, log2P; in getMNP_double() local
184 N2 = (clkP * M2 + calcclk1/2) / calcclk1; in getMNP_double()
185 if (N2 < minN2) in getMNP_double()
187 if (N2 > maxN2) in getMNP_double()
192 if (N2/M2 < 4 || N2/M2 > 10) in getMNP_double()
195 calcclk2 = calcclk1 * N2 / M2; in getMNP_double()
213 *pN2 = N2; in getMNP_double()
228 int *N1, int *M1, int *N2, int *M2, int *P) in nv04_pll_calc() argument
232 if (!info->vco2.max_freq || !N2) { in nv04_pll_calc()
234 if (N2) { in nv04_pll_calc()
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| D | nv40.c | 61 int N2 = (coef & 0xff000000) >> 24; in read_pll_2() local
72 khz = khz * N2 / M2; in read_pll_2()
125 int *N1, int *M1, int *N2, int *M2, int *log2P) in nv40_clk_calc_pll() argument
138 ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P); in nv40_clk_calc_pll()
151 int N1, M1, N2, M2, log2P; in nv40_clk_calc() local
156 &N1, &M1, &N2, &M2, &log2P); in nv40_clk_calc()
160 if (N2 == M2) { in nv40_clk_calc()
165 clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; in nv40_clk_calc()
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| D | nv04.c | 35 int N1, M1, N2, M2, P; in nv04_clk_pll_calc() local
36 int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P); in nv04_clk_pll_calc()
41 pv->N2 = N2; in nv04_clk_pll_calc()
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| D | pll.h | 9 int *N1, int *M1, int *N2, int *M2, int *P);
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| D | nv50.c | 166 int N1, N2, M1, M2; in read_pll() local
174 N2 = (coef & 0xff000000) >> 24; in read_pll()
182 freq = freq * N2 / M2; in read_pll()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | nv04.c | 210 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */ in setPLL_double_highregs()
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
217 (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4; in setPLL_double_highregs()
296 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; in setPLL_double_lowregs()
363 int N1, M1, N2, M2, P; in nv04_devinit_pll_set() local
370 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); in nv04_devinit_pll_set()
377 pv.N2 = N2; in nv04_devinit_pll_set()
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| D | nv50.c | 41 int N1, M1, N2, M2, P; in nv50_devinit_pll_set() local
50 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); in nv50_devinit_pll_set()
62 (M2 << 16) | N2); in nv50_devinit_pll_set()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | ramnv40.c | 40 int N1, M1, N2, M2; in nv40_ram_calc() local
49 ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P); in nv40_ram_calc()
55 if (N2 == M2) { in nv40_ram_calc()
60 ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; in nv40_ram_calc()
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| D | ramgk104.c | 134 int N2, M2, P2; member
160 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2); in r1373f4_init()
990 int *N2, int *M2, int *P2) in gk104_pll_calc_hiclk() argument
1013 *N2 = cur_N; in gk104_pll_calc_hiclk()
1024 *N2 = cur_N; in gk104_pll_calc_hiclk()
1033 *fN1 = (u16)((((best_err / *N2 * *P2) * (*P1 * *M1)) << 13) / crystal); in gk104_pll_calc_hiclk()
1067 &ram->N2, &ram->M2, &ram->P2); in gk104_ram_calc_xits()
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| D | ramnv50.c | 230 int N1, M1, N2, M2, P; in nv50_ram_calc() local
331 &N1, &M1, &N2, &M2, &P); in nv50_ram_calc()
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| /drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ |
| D | pll.h | 9 uint8_t N1, M1, N2, M2; member
11 uint8_t M1, N1, M2, N2;
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| /drivers/clk/pxa/ |
| D | clk-pxa25x.c | 34 #define PXA25x_CCCR(N2, M, L) (N2 << 7 | M << 5 | L) argument
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| D | clk-pxa27x.c | 51 #define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L) argument
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| /drivers/net/wan/ |
| D | Kconfig | 220 config N2 config
221 tristate "SDL RISCom/N2 support"
224 Driver for RISCom/N2 single or dual channel ISA cards by
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| /drivers/pinctrl/aspeed/ |
| D | pinctrl-aspeed-g4.c | 1543 #define N2 189 macro
1544 SIG_EXPR_LIST_DECL_SINGLE(N2, GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
1545 SIG_EXPR_LIST_DECL_SINGLE(N2, ADC13, ADC13);
1546 PIN_DECL_(N2, SIG_EXPR_LIST_PTR(N2, GPIOX5), SIG_EXPR_LIST_PTR(N2, ADC13));
1547 FUNC_GROUP_DECL(ADC13, N2);
2070 ASPEED_PINCTRL_PIN(N2),
2518 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N2, N2, SCUA8, 17),
2519 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N2, N2, SCUA8, 17),
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| D | pinctrl-aspeed-g5.c | 661 #define N2 83 macro
662 SIG_EXPR_LIST_DECL_SINGLE(N2, SDA6, I2C6, I2C6_DESC);
663 PIN_DECL_1(N2, GPIOK3, SDA6);
665 FUNC_GROUP_DECL(I2C6, L1, N2);
2059 ASPEED_PINCTRL_PIN(N2),
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | hw.c | 141 pllvals->N2 = pllvals->M2 = 1; in nouveau_hw_decode_pll()
156 pllvals->N2 = ((pll1 >> 21) & 0x18) | in nouveau_hw_decode_pll()
211 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P; in nouveau_hw_pllvals_to_clk()
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| D | crtc.c | 166 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); in nv_crtc_calc_state_ext()
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| /drivers/tty/ |
| D | n_gsm.c | 62 #define N2 3 /* Retry 3 times */ macro
2555 gsm->n2 = N2; in gsm_alloc_mux()
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| /drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/ |
| D | phy_lcn.c | 2000 u16 N1, N2, N3, N4, N5, N6, N; in wlc_lcnphy_rfseq_tbl_adc_pwrup() local
2003 N2 = 1 << ((read_phy_reg(pi, 0x4a5) & (0x7 << 12)) in wlc_lcnphy_rfseq_tbl_adc_pwrup()
2013 N = 2 * (N1 + N2 + N3 + N4 + 2 * (N5 + N6)) + 80; in wlc_lcnphy_rfseq_tbl_adc_pwrup()
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