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Searched refs:NUM_DCEFCLK_DPM_LEVELS (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/pm/inc/
Dsmu10_driver_if.h101 #define NUM_DCEFCLK_DPM_LEVELS 4 macro
111 DpmClock_t DcefClocks[NUM_DCEFCLK_DPM_LEVELS];
Dsmu9_driver_if.h43 #define NUM_DCEFCLK_DPM_LEVELS 8 macro
52 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
Dsmu11_driver_if.h44 #define NUM_DCEFCLK_DPM_LEVELS 8 macro
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
426 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ];
Dsmu11_driver_if_sienna_cichlid.h40 #define NUM_DCEFCLK_DPM_LEVELS 8 macro
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
668 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz
1027 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz
Dsmu11_driver_if_navi10.h41 #define NUM_DCEFCLK_DPM_LEVELS 8 macro
56 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
589 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz
/drivers/gpu/drm/amd/pm/inc/vega12/
Dsmu9_driver_if.h42 #define NUM_DCEFCLK_DPM_LEVELS 8 macro
55 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
313 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ];
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega20_processpptables.c341 for (i = 0; i < NUM_DCEFCLK_DPM_LEVELS; i++)
Dsmu10_hwmgr.c497 NUM_DCEFCLK_DPM_LEVELS, in smu10_populate_clock_table()