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Searched refs:NUM_DISPCLK_DPM_LEVELS (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/pm/inc/
Dsmu13_driver_if_yellow_carp.h104 #define NUM_DISPCLK_DPM_LEVELS 8 macro
123 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
Dsmu11_driver_if_vangogh.h104 #define NUM_DISPCLK_DPM_LEVELS 7 macro
129 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
Dsmu11_driver_if.h45 #define NUM_DISPCLK_DPM_LEVELS 8 macro
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
427 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ];
Dsmu11_driver_if_sienna_cichlid.h42 #define NUM_DISPCLK_DPM_LEVELS 8 macro
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
669 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz
1028 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz
Dsmu11_driver_if_navi10.h43 #define NUM_DISPCLK_DPM_LEVELS 8 macro
57 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
590 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
Ddcn31_smu.h106 #define NUM_DISPCLK_DPM_LEVELS 8 macro
132 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
Ddcn31_clk_mgr.c575 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn31_clk_mgr_helper_populate_bw_params()
/drivers/gpu/drm/amd/pm/inc/vega12/
Dsmu9_driver_if.h43 #define NUM_DISPCLK_DPM_LEVELS 8 macro
56 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
314 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ];
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega20_processpptables.c345 for (i = 0; i < NUM_DISPCLK_DPM_LEVELS; i++)