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Searched refs:NV_CIO_CRE_PIXEL_INDEX (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/nouveau/dispnv04/
Ddac.c166 saved_pi = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX); in nv04_dac_detect()
167 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, in nv04_dac_detect()
222 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi); in nv04_dac_detect()
Dcrtc.c578 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8; in nv_crtc_mode_set_regs()
581 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); in nv_crtc_mode_set_regs()
862 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; in nv04_crtc_do_mode_set_base()
863 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8; in nv04_crtc_do_mode_set_base()
867 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); in nv04_crtc_do_mode_set_base()
Dnvreg.h248 # define NV_CIO_CRE_PIXEL_INDEX 0x28 macro
Dhw.c602 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); in nv_save_state_ext()
716 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); in nv_load_state_ext()