Searched refs:NV_VIO_SR_CLOCK_INDEX (Results 1 – 5 of 5) sorted by relevance
| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | hw.h | 245 uint8_t seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); in NVVgaProtect()
249 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); in NVVgaProtect()
252 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); /* reenable display */ in NVVgaProtect()
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| D | dac.c | 157 saved_seq1 = NVReadVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX); in nv04_dac_detect()
158 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1 & ~0x20); in nv04_dac_detect()
224 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1); in nv04_dac_detect()
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| D | crtc.c | 226 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); in nv_crtc_dpms()
227 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); in nv_crtc_dpms()
335 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; in nv_crtc_mode_set_vga()
337 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; in nv_crtc_mode_set_vga()
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| D | nvreg.h | 133 # define NV_VIO_SR_CLOCK_INDEX 0x01 macro
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| D | hw.c | 117 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); in NVBlankScreen()
121 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); in NVBlankScreen()
123 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); in NVBlankScreen()
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