| /drivers/staging/rtl8723bs/core/ |
| D | rtw_efuse.c | 36 u16 Offset, in Efuse_Read1ByteFromFakeContent() argument
39 if (Offset >= EFUSE_MAX_HW_SIZE) in Efuse_Read1ByteFromFakeContent()
42 *Value = fakeEfuseContent[Offset]; in Efuse_Read1ByteFromFakeContent()
44 *Value = fakeBTEfuseContent[fakeEfuseBank-1][Offset]; in Efuse_Read1ByteFromFakeContent()
51 u16 Offset, in Efuse_Write1ByteToFakeContent() argument
54 if (Offset >= EFUSE_MAX_HW_SIZE) in Efuse_Write1ByteToFakeContent()
57 fakeEfuseContent[Offset] = Value; in Efuse_Write1ByteToFakeContent()
59 fakeBTEfuseContent[fakeEfuseBank-1][Offset] = Value; in Efuse_Write1ByteToFakeContent()
458 static void efuse_ShadowRead1Byte(struct adapter *padapter, u16 Offset, u8 *Value) in efuse_ShadowRead1Byte() argument
462 *Value = pEEPROM->efuse_eeprom_data[Offset]; in efuse_ShadowRead1Byte()
[all …]
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| /drivers/staging/r8188eu/core/ |
| D | rtw_efuse.c | 33 u16 Offset, in Efuse_Read1ByteFromFakeContent() argument
36 if (Offset >= EFUSE_MAX_HW_SIZE) in Efuse_Read1ByteFromFakeContent()
39 *Value = fakeEfuseContent[Offset]; in Efuse_Read1ByteFromFakeContent()
41 *Value = fakeBTEfuseContent[fakeEfuseBank - 1][Offset]; in Efuse_Read1ByteFromFakeContent()
48 u16 Offset, in Efuse_Write1ByteToFakeContent() argument
51 if (Offset >= EFUSE_MAX_HW_SIZE) in Efuse_Write1ByteToFakeContent()
54 fakeEfuseContent[Offset] = Value; in Efuse_Write1ByteToFakeContent()
56 fakeBTEfuseContent[fakeEfuseBank - 1][Offset] = Value; in Efuse_Write1ByteToFakeContent()
723 u16 Offset, in efuse_ShadowRead1Byte() argument
728 *Value = pEEPROM->efuse_eeprom_data[Offset]; in efuse_ShadowRead1Byte()
[all …]
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| /drivers/mtd/ |
| D | ftl.c | 116 uint32_t Offset; member
122 uint32_t Offset; member
209 part->EUNInfo[i].Offset = 0xffffffff; in build_maps()
231 (part->EUNInfo[le16_to_cpu(header.LogicalEUN)].Offset == 0xffffffff)) { in build_maps()
232 part->EUNInfo[le16_to_cpu(header.LogicalEUN)].Offset = offset; in build_maps()
251 part->XferInfo[xtrans].Offset = offset; in build_maps()
284 offset = part->EUNInfo[i].Offset + le32_to_cpu(header.BAMOffset); in build_maps()
336 pr_debug("ftl_cs: erasing xfer unit at 0x%x\n", xfer->Offset); in erase_xfer()
346 erase->addr = xfer->Offset; in erase_xfer()
382 pr_debug("ftl_cs: preparing xfer unit at 0x%x\n", xfer->Offset); in prepare_xfer()
[all …]
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| /drivers/staging/r8188eu/hal/ |
| D | rtl8188e_phycfg.c | 142 u32 Offset in phy_RFSerialRead() argument
154 Offset &= 0xff; in phy_RFSerialRead()
159 NewOffset = Offset; in phy_RFSerialRead()
240 u32 Offset, in phy_RFSerialWrite() argument
251 Offset &= 0xff; in phy_RFSerialWrite()
256 NewOffset = Offset; in phy_RFSerialWrite()
660 int Offset = 0; in phy_DbmToTxPwrIdx() local
671 Offset = -7; in phy_DbmToTxPwrIdx()
677 Offset = -8; in phy_DbmToTxPwrIdx()
681 if ((PowerInDbm - Offset) > 0) in phy_DbmToTxPwrIdx()
[all …]
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| /drivers/staging/rtl8192e/rtl8192e/ |
| D | r8192E_phy.c | 38 enum rf90_radio_path eRFPath, u32 Offset);
40 enum rf90_radio_path eRFPath, u32 Offset,
92 enum rf90_radio_path eRFPath, u32 Offset) in _rtl92e_phy_rf_read() argument
99 Offset &= 0x3f; in _rtl92e_phy_rf_read()
103 if (Offset >= 31) { in _rtl92e_phy_rf_read()
108 NewOffset = Offset - 30; in _rtl92e_phy_rf_read()
109 } else if (Offset >= 16) { in _rtl92e_phy_rf_read()
116 NewOffset = Offset - 15; in _rtl92e_phy_rf_read()
118 NewOffset = Offset; in _rtl92e_phy_rf_read()
122 NewOffset = Offset; in _rtl92e_phy_rf_read()
[all …]
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| D | r8192E_phy.h | 79 enum ht_extchnl_offset Offset);
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| D | r8190P_def.h | 207 u8 Offset; member
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| D | r8192E_dev.c | 1225 pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8; in rtl92e_fill_tx_desc()
1298 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8; in rtl92e_fill_tx_cmd_desc()
1300 entry_tmp->Offset); in rtl92e_fill_tx_cmd_desc()
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| /drivers/staging/rtl8723bs/hal/ |
| D | rtl8723b_phycfg.c | 93 struct adapter *Adapter, enum rf_path eRFPath, u32 Offset in phy_RFSerialRead_8723B() argument
108 Offset &= 0xff; in phy_RFSerialRead_8723B()
110 NewOffset = Offset; in phy_RFSerialRead_8723B()
188 u32 Offset, in phy_RFSerialWrite_8723B() argument
197 Offset &= 0xff; in phy_RFSerialWrite_8723B()
202 NewOffset = Offset; in phy_RFSerialWrite_8723B()
771 unsigned char Offset /* Upper, Lower, or Don't care */ in PHY_SetBWMode8723B() argument
776 …etBW8723B(Adapter, false, true, pHalData->CurrentChannel, Bandwidth, Offset, Offset, pHalData->Cur… in PHY_SetBWMode8723B()
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| /drivers/staging/rtl8192e/ |
| D | rtl819x_HTProc.c | 510 enum ht_extchnl_offset Offset);
858 enum ht_extchnl_offset Offset) in HTSetConnectBwMode() argument
874 Offset == HT_EXTCHNL_OFFSET_LOWER) in HTSetConnectBwMode()
875 Offset = HT_EXTCHNL_OFFSET_NO_EXT; in HTSetConnectBwMode()
876 if (Offset == HT_EXTCHNL_OFFSET_UPPER || in HTSetConnectBwMode()
877 Offset == HT_EXTCHNL_OFFSET_LOWER) { in HTSetConnectBwMode()
879 pHTInfo->CurSTAExtChnlOffset = Offset; in HTSetConnectBwMode()
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| D | rtllib.h | 1769 enum ht_extchnl_offset Offset);
2077 enum ht_extchnl_offset Offset);
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| /drivers/staging/rtl8192u/ieee80211/ |
| D | rtl819x_HTProc.c | 1252 …ruct ieee80211_device *ieee, enum ht_channel_width Bandwidth, enum ht_extension_chan_offset Offset) in HTSetConnectBwMode() argument
1273 if (ieee->current_network.channel < 2 && Offset == HT_EXTCHNL_OFFSET_LOWER) in HTSetConnectBwMode()
1274 Offset = HT_EXTCHNL_OFFSET_NO_EXT; in HTSetConnectBwMode()
1275 if (Offset == HT_EXTCHNL_OFFSET_UPPER || Offset == HT_EXTCHNL_OFFSET_LOWER) { in HTSetConnectBwMode()
1277 pHTInfo->CurSTAExtChnlOffset = Offset; in HTSetConnectBwMode()
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| /drivers/staging/rtl8723bs/include/ |
| D | hal_phy_cfg.h | 57 unsigned char Offset);
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| D | rtw_efuse.h | 120 void EFUSE_ShadowRead(struct adapter *padapter, u8 Type, u16 Offset, u32 *Value);
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| D | hal_intf.h | 197 void (*set_bwmode_handler)(struct adapter *padapter, enum channel_width Bandwidth, u8 Offset);
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| /drivers/video/fbdev/riva/ |
| D | riva_hw.c | 1845 NV_WR32(&Surface->Offset, 0, surf0); in nv3SetSurfaces2D()
1847 NV_WR32(&Surface->Offset, 0, surf1); in nv3SetSurfaces2D()
1861 NV_WR32(&Surface->Offset, 0, surf0); in nv4SetSurfaces2D()
1863 NV_WR32(&Surface->Offset, 0, surf1); in nv4SetSurfaces2D()
1877 NV_WR32(&Surface->Offset, 0, surf0); in nv10SetSurfaces2D()
1879 NV_WR32(&Surface->Offset, 0, surf1); in nv10SetSurfaces2D()
1894 NV_WR32(&Surface->Offset, 0, surf0); in nv3SetSurfaces3D()
1896 NV_WR32(&Surface->Offset, 0, surf1); in nv3SetSurfaces3D()
1910 NV_WR32(&Surface->Offset, 0, surf0); in nv4SetSurfaces3D()
1912 NV_WR32(&Surface->Offset, 0, surf1); in nv4SetSurfaces3D()
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| D | riva_hw.h | 390 U032 Offset; member
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| /drivers/staging/r8188eu/include/ |
| D | hal_intf.h | 165 u8 Offset);
383 enum ht_channel_width Bandwidth, u8 Offset);
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| /drivers/scsi/aic7xxx/ |
| D | aic79xx.reg | 277 * Host New SCB Queue Offset
288 * Host Empty SCB Queue Offset
346 * SEQ New SCB Queue Offset
357 * SEQ Empty SCB Queue Offset
368 * SEQ Done SCB Queue Offset
379 * Queue Offset Control & Status
1390 * Offset to the SCB flags field that includes the
1923 field OVERRUN 0x04 /* SCSI Offset overrun detected */
2076 * SCSI Offset Count
2628 * Data Transfer Negotiation Data - Offset Byte
[all …]
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| /drivers/scsi/mpt3sas/mpi/ |
| D | mpi2_image.h | 161 U32 Offset; /*0x00 */ member
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| /drivers/thermal/intel/ |
| D | Kconfig | 89 activation temperature via the TCC Offset register, which is widely
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| /drivers/net/ethernet/atheros/atlx/ |
| D | atl2.h | 79 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue);
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| D | atl2.c | 2706 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue) in atl2_read_eeprom() argument
2711 if (Offset & 0x3) in atl2_read_eeprom()
2715 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; in atl2_read_eeprom()
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| /drivers/message/fusion/ |
| D | mptbase.h | 227 u8 Offset; /* 00h */ member
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| /drivers/net/wireless/marvell/libertas/ |
| D | README | 55 Offset Values
|