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Searched refs:P (Results 1 – 25 of 72) sorted by relevance

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/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dnv50.c58 int P, N, M, id; in read_pll_src() local
75 P = (coef & 0x00070000) >> 16; in read_pll_src()
83 P = (coef & 0x00070000) >> 16; in read_pll_src()
109 P = (nvkm_rd32(device, 0x00e824 + (id * 0x28)) >> 16) & 7; in read_pll_src()
110 P += (coef & 0x00070000) >> 16; in read_pll_src()
119 return (ref * N / M) >> P; in read_pll_src()
198 u32 P = 0; in nv50_clk_read() local
221 P = (nvkm_rd32(device, 0x004028) & 0x00070000) >> 16; in nv50_clk_read()
223 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; in nv50_clk_read()
225 case 0x00000002: return read_pll(clk, 0x004020) >> P; in nv50_clk_read()
[all …]
Dpllgt215.c31 u32 freq, int *pN, int *pfN, int *pM, int *P) in gt215_pll_calc() argument
36 *P = info->vco1.max_freq / freq; in gt215_pll_calc()
37 if (*P > info->max_p) in gt215_pll_calc()
38 *P = info->max_p; in gt215_pll_calc()
39 if (*P < info->min_p) in gt215_pll_calc()
40 *P = info->min_p; in gt215_pll_calc()
49 u32 tmp = freq * *P * M; in gt215_pll_calc()
67 err = abs(freq - (info->refclk * N / M / *P)); in gt215_pll_calc()
86 return info->refclk * *pN / *pM / *P; in gt215_pll_calc()
Dmcp77.c87 u32 P = 0; in mcp77_clk_read() local
107 P = (nvkm_rd32(device, 0x004028) & 0x00070000) >> 16; in mcp77_clk_read()
110 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; in mcp77_clk_read()
112 case 0x00000002: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4) >> P; in mcp77_clk_read()
113 case 0x00000003: return read_pll(clk, 0x004028) >> P; in mcp77_clk_read()
130 P = (nvkm_rd32(device, 0x004020) & 0x00070000) >> 16; in mcp77_clk_read()
134 return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P; in mcp77_clk_read()
135 return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; in mcp77_clk_read()
137 case 0x00000020: return read_pll(clk, 0x004028) >> P; in mcp77_clk_read()
138 case 0x00000030: return read_pll(clk, 0x004020) >> P; in mcp77_clk_read()
[all …]
Dpllnv04.c49 int M, N, thisP, P; in getMNP_single() local
73 P = 1 << maxP; in getMNP_single()
74 if ((clk * P) < minvco) { in getMNP_single()
84 P = 1 << thisP; in getMNP_single()
85 clkP = clk * P; in getMNP_single()
107 calcclk = ((N * crystal + P/2) / P + M/2) / M; in getMNP_single()
228 int *N1, int *M1, int *N2, int *M2, int *P) in nv04_pll_calc() argument
233 ret = getMNP_single(subdev, info, freq, N1, M1, P); in nv04_pll_calc()
239 ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P); in nv04_pll_calc()
Dgk104.c65 u32 P = (coef & 0x003f0000) >> 16; in read_pll() local
78 P = 1; in read_pll()
82 P = (coef & 0x10000000) ? 2 : 1; in read_pll()
98 if (P == 0) in read_pll()
99 P = 1; in read_pll()
102 return sclk / (M * P); in read_pll()
268 int N, M, P, ret; in calc_pll() local
278 ret = gt215_pll_calc(subdev, &limits, freq, &N, NULL, &M, &P); in calc_pll()
282 *coef = (P << 16) | (N << 8) | M; in calc_pll()
Dnv04.c35 int N1, M1, N2, M2, P; in nv04_clk_pll_calc() local
36 int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P); in nv04_clk_pll_calc()
43 pv->log2P = P; in nv04_clk_pll_calc()
Dgt215.c112 u32 sclk = 0, P = 1, N = 1, M = 1; in read_pll() local
120 P = (coef & 0x003f0000) >> 16; in read_pll()
126 P = 1; in read_pll()
134 MP = M * P; in read_pll()
241 int P, N, M, diff; in gt215_pll_info() local
263 ret = gt215_pll_calc(subdev, &limits, khz, &N, NULL, &M, &P); in gt215_pll_info()
265 info->pll = (P << 16) | (N << 8) | M; in gt215_pll_info()
Dpll.h9 int *N1, int *M1, int *N2, int *M2, int *P);
11 int *N, int *fN, int *M, int *P);
Dnv40.c44 int P = (ctrl & 0x00070000) >> 16; in read_pll_1() local
52 return khz >> P; in read_pll_1()
65 int P = (ctrl & 0x00070000) >> 16; in read_pll_2() local
78 return khz >> P; in read_pll_2()
Dgf100.c64 u32 P = (coef & 0x003f0000) >> 16; in read_pll() local
76 P = 1; in read_pll()
94 return sclk * N / M / P; in read_pll()
255 int N, M, P, ret; in calc_pll() local
265 ret = gt215_pll_calc(subdev, &limits, freq, &N, NULL, &M, &P); in calc_pll()
269 *coef = (P << 16) | (N << 8) | M; in calc_pll()
/drivers/isdn/mISDN/
Ddsp_blowfish.c360 #define EROUND(a, b, n) do { b ^= P[n]; a ^= bf_F(b); } while (0)
361 #define DROUND(a, b, n) do { a ^= bf_F(b); b ^= P[n]; } while (0)
374 u32 *P = dsp->bf_p; in dsp_bf_encrypt() local
422 yl ^= P[16]; in dsp_bf_encrypt()
423 yr ^= P[17]; in dsp_bf_encrypt()
466 u32 *P = dsp->bf_p; in dsp_bf_decrypt() local
520 yr ^= P[17]; in dsp_bf_decrypt()
521 yl ^= P[16]; in dsp_bf_decrypt()
563 encrypt_block(const u32 *P, const u32 *S, u32 *dst, u32 *src) in encrypt_block() argument
585 yl ^= P[16]; in encrypt_block()
[all …]
/drivers/gpu/drm/i915/display/
Dintel_overlay.c1486 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) in intel_overlay_print_error_state() macro
1487 P(OBUF_0Y); in intel_overlay_print_error_state()
1488 P(OBUF_1Y); in intel_overlay_print_error_state()
1489 P(OBUF_0U); in intel_overlay_print_error_state()
1490 P(OBUF_0V); in intel_overlay_print_error_state()
1491 P(OBUF_1U); in intel_overlay_print_error_state()
1492 P(OBUF_1V); in intel_overlay_print_error_state()
1493 P(OSTRIDE); in intel_overlay_print_error_state()
1494 P(YRGB_VPH); in intel_overlay_print_error_state()
1495 P(UV_VPH); in intel_overlay_print_error_state()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv50.c41 int N1, M1, N2, M2, P; in nv50_devinit_pll_set() local
50 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); in nv50_devinit_pll_set()
61 nvkm_mask(device, info.reg + 8, 0x7fff00ff, (P << 28) | in nv50_devinit_pll_set()
66 (P << 22) | in nv50_devinit_pll_set()
68 (P << 16)); in nv50_devinit_pll_set()
72 nvkm_mask(device, info.reg + 0, 0x00070000, (P << 16)); in nv50_devinit_pll_set()
Dga100.c35 int N, fN, M, P; in ga100_devinit_pll_set() local
42 ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P); in ga100_devinit_pll_set()
53 nvkm_wr32(device, 0x00ef04 + (head * 0x40), (P << 16) | M); in ga100_devinit_pll_set()
Dgv100.c35 int N, fN, M, P; in gv100_devinit_pll_set() local
42 ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P); in gv100_devinit_pll_set()
52 nvkm_wr32(device, 0x00ef04 + (head * 0x40), (P << 16) | in gv100_devinit_pll_set()
Dtu102.c35 int N, fN, M, P; in tu102_devinit_pll_set() local
42 ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P); in tu102_devinit_pll_set()
52 nvkm_wr32(device, 0x00ef04 + (head * 0x40), (P << 16) | in tu102_devinit_pll_set()
Dgf100.c37 int N, fN, M, P; in gf100_devinit_pll_set() local
44 ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P); in gf100_devinit_pll_set()
54 nvkm_wr32(device, info.reg + 0x04, (P << 16) | (N << 8) | M); in gf100_devinit_pll_set()
Dgt215.c37 int N, fN, M, P; in gt215_devinit_pll_set() local
44 ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P); in gt215_devinit_pll_set()
53 (P << 16) | (M << 8) | N); in gt215_devinit_pll_set()
/drivers/video/fbdev/nvidia/
Dnv_hw.c144 unsigned int pll, N, M, MB, NB, P; in nvGetClocks() local
148 P = (pll >> 16) & 0x07; in nvGetClocks()
160 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; in nvGetClocks()
163 P = (pll >> 16) & 0x07; in nvGetClocks()
170 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; in nvGetClocks()
175 P = (pll >> 16) & 0x0F; in nvGetClocks()
184 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; in nvGetClocks()
189 P = (pll >> 16) & 0x0F; in nvGetClocks()
198 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; in nvGetClocks()
205 P = (pll >> 16) & 0x07; in nvGetClocks()
[all …]
/drivers/gpu/drm/i2c/
Dch7006_mode.c164 __MODE(29500, 720, 576, 944, 625, P, P, 145.592111636, 1_1, 0x7, PAL_LIKE, 800, 600),
165 MODE(36000, 800, 600, 960, 750, P, P, 119.304647022, 5_6, 0x6, PAL_LIKE),
166 MODE(39000, 800, 600, 936, 836, P, P, 110.127366499, 3_4, 0x1, PAL_LIKE),
167 MODE(39273, 800, 600, 1040, 630, P, P, 145.816809399, 5_6, 0x4, NTSC_LIKE),
168 MODE(43636, 800, 600, 1040, 700, P, P, 131.235128487, 3_4, 0x2, NTSC_LIKE),
169 MODE(47832, 800, 600, 1064, 750, P, P, 119.723275165, 7_10, 0x1, NTSC_LIKE),
/drivers/regulator/
Dmax77620-regulator.c734 RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000),
735 RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
736 RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
737 RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
738 RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
752 RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000),
753 RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
754 RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
755 RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
756 RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
[all …]
/drivers/block/paride/
Dmkd16 for P in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
17 do mkdev pd$D$P b 45 $[ $1 * 16 + $P ]
/drivers/net/ethernet/intel/ixgbe/
Dixgbe_type.h2531 #define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P))) argument
2532 #define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P))) argument
2533 #define IXGBE_PVFTXDCTL(P) (0x06028 + (0x40 * (P))) argument
2534 #define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P))) argument
2535 #define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P))) argument
3665 #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010) argument
3666 #define IXGBE_KRM_LINK_S1(P) ((P) ? 0x8200 : 0x4200) argument
3667 #define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C) argument
3668 #define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C) argument
3669 #define IXGBE_KRM_AN_CNTL_8(P) ((P) ? 0x8248 : 0x4248) argument
[all …]
/drivers/video/fbdev/kyro/
DSTG4000Ramdac.c30 u32 F = 0, R = 0, P = 0; in InitialiseRamdac() local
87 *pixelClock = ProgramClock(REF_CLOCK, *pixelClock, &F, &R, &P); in InitialiseRamdac()
93 tmp |= ((P) | ((F - 2) << 2) | ((R - 2) << 11)); in InitialiseRamdac()
/drivers/video/fbdev/riva/
Driva_hw.c618 unsigned int M, N, P, pll, MClk; in nv3UpdateArbitrationSettings() local
621 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv3UpdateArbitrationSettings()
622 MClk = (N * chip->CrystalFreqKHz / M) >> P; in nv3UpdateArbitrationSettings()
802 unsigned int M, N, P, pll, MClk, NVClk, cfg1; in nv4UpdateArbitrationSettings() local
805 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv4UpdateArbitrationSettings()
806 MClk = (N * chip->CrystalFreqKHz / M) >> P; in nv4UpdateArbitrationSettings()
808 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv4UpdateArbitrationSettings()
809 NVClk = (N * chip->CrystalFreqKHz / M) >> P; in nv4UpdateArbitrationSettings()
1051 unsigned int M, N, P, pll, MClk, NVClk, cfg1; in nv10UpdateArbitrationSettings() local
1054 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv10UpdateArbitrationSettings()
[all …]

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