| /drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v1_0.c | 222 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v1_0_enable_system_domain()
265 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v1_0_setup_vmid_config()
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| D | gfxhub_v2_0.c | 260 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gfxhub_v2_0_enable_system_domain()
292 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v2_0_setup_vmid_config()
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| D | gfxhub_v2_1.c | 263 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gfxhub_v2_1_enable_system_domain()
301 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v2_1_setup_vmid_config()
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| D | mmhub_v2_0.c | 335 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in mmhub_v2_0_enable_system_domain()
376 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in mmhub_v2_0_setup_vmid_config()
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| D | mmhub_v2_3.c | 254 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in mmhub_v2_3_enable_system_domain()
289 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in mmhub_v2_3_setup_vmid_config()
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| D | mmhub_v1_0.c | 203 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in mmhub_v1_0_enable_system_domain()
247 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in mmhub_v1_0_setup_vmid_config()
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| D | gmc_v7_0.c | 667 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gmc_v7_0_gart_enable()
697 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); in gmc_v7_0_gart_enable()
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| D | mmhub_v1_7.c | 232 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, in mmhub_v1_7_enable_system_domain()
279 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in mmhub_v1_7_setup_vmid_config()
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| D | gmc_v8_0.c | 906 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gmc_v8_0_gart_enable()
936 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); in gmc_v8_0_gart_enable()
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| D | mmhub_v9_4.c | 263 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in mmhub_v9_4_enable_system_domain()
307 PAGE_TABLE_DEPTH, in mmhub_v9_4_setup_vmid_config()
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| D | sid.h | 395 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) macro
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| /drivers/gpu/drm/radeon/ |
| D | rv770d.h | 636 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) macro
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| D | ni.c | 1298 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cayman_pcie_gart_enable()
1322 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cayman_pcie_gart_enable()
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| D | nid.h | 129 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) macro
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| D | sid.h | 394 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) macro
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| D | cikd.h | 512 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) macro
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| D | rv770.c | 939 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in rv770_pcie_gart_enable()
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| D | evergreend.h | 1138 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) macro
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| D | r600d.h | 575 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) macro
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| D | si.c | 4321 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in si_pcie_gart_enable()
4349 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in si_pcie_gart_enable()
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| D | cik.c | 5456 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cik_pcie_gart_enable()
5480 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cik_pcie_gart_enable()
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| D | r600.c | 1171 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in r600_pcie_gart_enable()
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| D | evergreen.c | 2442 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in evergreen_pcie_gart_enable()
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