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Searched refs:PIPE_A (Results 1 – 25 of 35) sorted by relevance

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/drivers/gpu/drm/i915/gvt/
Dhandlers.c691 vgpu->id, pipe_name(PIPE_A), new_rate); in vgpu_update_refresh_rate()
2285 MMIO_D(PIPEDSL(PIPE_A), D_ALL); in init_generic_mmio_info()
2290 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2295 MMIO_D(PIPESTAT(PIPE_A), D_ALL); in init_generic_mmio_info()
2300 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); in init_generic_mmio_info()
2305 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); in init_generic_mmio_info()
2310 MMIO_D(CURCNTR(PIPE_A), D_ALL); in init_generic_mmio_info()
2314 MMIO_D(CURPOS(PIPE_A), D_ALL); in init_generic_mmio_info()
2318 MMIO_D(CURBASE(PIPE_A), D_ALL); in init_generic_mmio_info()
2322 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL); in init_generic_mmio_info()
[all …]
Ddisplay.c46 pipe = PIPE_A; in get_edp_pipe()
75 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()
247 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
248 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE; in emulate_monitor_status_change()
505 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
623 [PIPE_A] = PIPE_A_VBLANK, in emulate_vblank_on_pipe()
629 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()
Dreg.h72 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
82 (((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
/drivers/gpu/drm/i915/
Di915_pci.c97 [PIPE_A] = CURSOR_A_OFFSET, \
102 [PIPE_A] = CURSOR_A_OFFSET, \
108 [PIPE_A] = CURSOR_A_OFFSET, \
115 [PIPE_A] = CURSOR_A_OFFSET, \
122 [PIPE_A] = CURSOR_A_OFFSET, \
160 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
181 .pipe_mask = BIT(PIPE_A), \
223 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
313 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
366 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
[all …]
Dintel_pm.c510 case PIPE_A: in vlv_get_fifo_size()
997 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in g4x_write_wm_values()
1003 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in g4x_write_wm_values()
1004 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in g4x_write_wm_values()
1047 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in vlv_write_wm_values()
1049 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | in vlv_write_wm_values()
1050 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in vlv_write_wm_values()
1051 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in vlv_write_wm_values()
1073 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
1074 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
[all …]
Dintel_device_info.c272 runtime->num_scalers[PIPE_A] = 2; in intel_device_info_runtime_init()
298 runtime->num_sprites[PIPE_A] = 2; in intel_device_info_runtime_init()
340 info->pipe_mask &= ~BIT(PIPE_A); in intel_device_info_runtime_init()
Di915_trace.h45 __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
72 __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
169 __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
Di915_irq.c583 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat()
1428 case PIPE_A: in i9xx_pipestat_irq_ack()
1863 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); in ibx_irq_handler()
2397 pipe = PIPE_A; in gen11_dsi_te_interrupt_handler()
3026 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in vlv_display_irq_postinstall()
3943 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
4122 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
4242 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_irq_postinstall()
4243 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
/drivers/gpu/drm/i915/display/
Dintel_fdi.c54 case PIPE_A: in ilk_check_fdi_lanes()
582 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
589 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
590 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
595 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
622 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); in hsw_fdi_link_train()
626 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
627 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
633 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
635 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); in hsw_fdi_link_train()
[all …]
Dg4x_hdmi.c323 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
324 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
327 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_hdmi()
341 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_disable_hdmi()
342 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
343 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
596 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
Dintel_cursor.c285 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); in i845_update_cursor()
286 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); in i845_update_cursor()
288 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); in i845_update_cursor()
289 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); in i845_update_cursor()
295 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); in i845_update_cursor()
315 power_domain = POWER_DOMAIN_PIPE(PIPE_A); in i845_cursor_get_hw_state()
320 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE; in i845_cursor_get_hw_state()
322 *pipe = PIPE_A; in i845_cursor_get_hw_state()
Dg4x_dp.c285 *pipe = PIPE_A; in cpt_dp_port_selected()
463 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down()
464 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down()
468 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | in intel_dp_link_down()
477 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_dp_link_down()
478 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_dp_link_down()
479 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_dp_link_down()
1395 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
Dintel_crt.c242 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_disable_crt()
271 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_post_disable_crt()
283 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_pre_pll_enable_crt()
328 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_enable_crt()
1049 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1115 FDI_RX_CTL(PIPE_A)) & fdi_config; in intel_crt_init()
Dintel_pipe_crc.c180 case PIPE_A: in vlv_pipe_crc_ctl_reg()
244 case PIPE_A: in vlv_undo_pipe_scramble_reset()
317 pipe_config->hw.active && crtc->pipe == PIPE_A && in intel_crtc_crc_setup_workarounds()
Dintel_fifo_underrun.c136 u32 bit = (pipe == PIPE_A) ? in ilk_set_fifo_underrun_reporting()
223 u32 bit = (pch_transcoder == PIPE_A) ? in ibx_set_fifo_underrun_reporting()
Dintel_dpll.c1117 if (crtc->pipe != PIPE_A) in vlv_compute_dpll()
1134 if (crtc->pipe != PIPE_A) in chv_compute_dpll()
1529 if (pipe != PIPE_A) { in chv_enable_pll()
1628 if (pipe == PIPE_A) in vlv_prepare_pll()
1636 if (pipe == PIPE_A) in vlv_prepare_pll()
1808 if (pipe != PIPE_A) in vlv_disable_pll()
1825 if (pipe != PIPE_A) in chv_disable_pll()
Dintel_pps.c125 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
182 pipe = PIPE_A; in vlv_power_sequencer_pipe()
259 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
955 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
Dintel_ddi.c459 case PIPE_A: in intel_ddi_transcoder_func_reg_val_get()
730 *pipe_mask = BIT(PIPE_A); in intel_ddi_get_encoder_pipes()
2259 return BIT(PIPE_A) | BIT(PIPE_B); in intel_ddi_splitter_pipe_mask()
2261 return BIT(PIPE_A); in intel_ddi_splitter_pipe_mask()
2937 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); in intel_ddi_fdi_post_disable()
2939 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); in intel_ddi_fdi_post_disable()
2944 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); in intel_ddi_fdi_post_disable()
2947 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val); in intel_ddi_fdi_post_disable()
2949 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); in intel_ddi_fdi_post_disable()
2951 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); in intel_ddi_fdi_post_disable()
[all …]
Dintel_vdsc.c352 (pipe != PIPE_A || cpu_transcoder == TRANSCODER_EDP || in intel_dsc_source_support()
375 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); in is_pipe_dsc()
567 if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A) in intel_dsc_power_domain()
Dintel_display_power.c1262 if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1263 i830_enable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_enable()
1272 i830_disable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_disable()
1278 return intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE && in i830_pipes_power_well_enabled()
1421 if (pipe != PIPE_A) in vlv_display_power_well_init()
1646 pipe = PIPE_A; in chv_dpio_cmn_power_well_enable()
1710 assert_pll_disabled(dev_priv, PIPE_A); in chv_dpio_cmn_power_well_disable()
1736 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; in assert_chv_phy_powergate()
1865 enum pipe pipe = PIPE_A; in chv_pipe_power_well_enabled()
1896 enum pipe pipe = PIPE_A; in chv_set_pipe_power_well()
[all …]
Dintel_display.h87 PIPE_A = 0, enumerator
106 TRANSCODER_A = PIPE_A,
Dintel_sdvo.c1788 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_sdvo()
1789 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_sdvo()
1792 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_sdvo()
1798 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_disable_sdvo()
1799 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_sdvo()
1800 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_sdvo()
Dintel_display.c686 assert_fdi_rx_enabled(dev_priv, PIPE_A); in lpt_enable_pch_transcoder()
688 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); in lpt_enable_pch_transcoder()
694 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); in lpt_enable_pch_transcoder()
755 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); in lpt_disable_pch_transcoder()
757 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); in lpt_disable_pch_transcoder()
765 return PIPE_A; in intel_crtc_pch_transcoder()
2265 case PIPE_A: in ivb_update_fdi_bc_bifurcation()
2411 assert_pch_transcoder_disabled(dev_priv, PIPE_A); in lpt_pch_enable()
2416 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A); in lpt_pch_enable()
3216 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; in hsw_crtc_supports_ips()
[all …]
/drivers/video/fbdev/intelfb/
Dintelfbhw.c482 if (unlikely(pipe == PIPE_A)) in intelfbhw_active_pipe()
483 return PIPE_A; in intelfbhw_active_pipe()
488 if (likely(pipe == PIPE_A)) in intelfbhw_active_pipe()
489 return PIPE_A; in intelfbhw_active_pipe()
494 pipe = PIPE_A; in intelfbhw_active_pipe()
503 u32 palette_reg = (dinfo->pipe == PIPE_A) ? in intelfbhw_setcolreg()
Dintelfbhw.h182 #define PIPE_A 0 macro

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