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Searched refs:PIPE_B (Results 1 – 25 of 34) sorted by relevance

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/drivers/gpu/drm/i915/gvt/
Dhandlers.c2286 MMIO_D(PIPEDSL(PIPE_B), D_ALL); in init_generic_mmio_info()
2291 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2296 MMIO_D(PIPESTAT(PIPE_B), D_ALL); in init_generic_mmio_info()
2301 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); in init_generic_mmio_info()
2306 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); in init_generic_mmio_info()
2311 MMIO_D(CURCNTR(PIPE_B), D_ALL); in init_generic_mmio_info()
2315 MMIO_D(CURPOS(PIPE_B), D_ALL); in init_generic_mmio_info()
2319 MMIO_D(CURBASE(PIPE_B), D_ALL); in init_generic_mmio_info()
2323 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL); in init_generic_mmio_info()
2346 MMIO_D(DSPCNTR(PIPE_B), D_ALL); in init_generic_mmio_info()
[all …]
Dreg.h74 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
83 (((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
Ddisplay.c49 pipe = PIPE_B; in get_edp_pipe()
624 [PIPE_B] = PIPE_B_VBLANK, in emulate_vblank_on_pipe()
Dinterrupt.c454 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B));
Dcmd_parser.c1286 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE}, in gen8_decode_mi_display_flip()
1288 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE}, in gen8_decode_mi_display_flip()
1344 info->pipe = PIPE_B; in skl_decode_mi_display_flip()
1358 info->pipe = PIPE_B; in skl_decode_mi_display_flip()
/drivers/gpu/drm/i915/
Di915_pci.c103 [PIPE_B] = CURSOR_B_OFFSET, \
109 [PIPE_B] = CURSOR_B_OFFSET, \
116 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
123 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
160 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
223 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
313 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
366 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
396 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
448 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
[all …]
Dintel_pm.c516 case PIPE_B: in vlv_get_fifo_size()
995 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in g4x_write_wm_values()
996 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in g4x_write_wm_values()
1002 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | in g4x_write_wm_values()
1045 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in vlv_write_wm_values()
1046 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in vlv_write_wm_values()
1057 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | in vlv_write_wm_values()
1058 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); in vlv_write_wm_values()
1070 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
1071 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
[all …]
Di915_reg.h4731 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4734 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4737 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4740 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4759 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4762 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4765 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4768 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4784 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4787 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
[all …]
Dintel_device_info.c273 runtime->num_scalers[PIPE_B] = 2; in intel_device_info_runtime_init()
299 runtime->num_sprites[PIPE_B] = 2; in intel_device_info_runtime_init()
344 info->pipe_mask &= ~BIT(PIPE_B); in intel_device_info_runtime_init()
Di915_trace.h46 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
73 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
170 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
Di915_irq.c581 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
1431 case PIPE_B: in i9xx_pipestat_irq_ack()
1866 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); in ibx_irq_handler()
2400 pipe = PIPE_B; in gen11_dsi_te_interrupt_handler()
3944 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
4123 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
4244 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
/drivers/gpu/drm/i915/display/
Dintel_dpio_phy.c806 if (ch == DPIO_CH0 && pipe == PIPE_B) in chv_phy_pre_pll_enable()
818 if (pipe != PIPE_B) { in chv_phy_pre_pll_enable()
839 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
848 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
861 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
971 if (pipe != PIPE_B) { in chv_phy_post_pll_disable()
Dintel_pipe_crc.c183 case PIPE_B: in vlv_pipe_crc_ctl_reg()
247 case PIPE_B: in vlv_undo_pipe_scramble_reset()
Dintel_display_power.c1264 if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1265 i830_enable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_enable()
1271 i830_disable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_disable()
1279 intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in i830_pipes_power_well_enabled()
1581 (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
1711 assert_pll_disabled(dev_priv, PIPE_B); in chv_dpio_cmn_power_well_disable()
3247 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3448 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3530 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3590 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
[all …]
Dg4x_hdmi.c318 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { in intel_disable_hdmi()
596 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
Dintel_display.h88 PIPE_B, enumerator
107 TRANSCODER_B = PIPE_B,
Dintel_pps.c125 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
259 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
955 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
Dintel_fdi.c56 case PIPE_B: in ilk_check_fdi_lanes()
81 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); in ilk_check_fdi_lanes()
Di9xx_plane.c896 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_primary_plane_create()
1000 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && in i9xx_get_initial_plane_config()
Dicl_dsi.c874 case PIPE_B: in gen11_dsi_configure_transcoder()
1275 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B) in icl_apply_kvmr_pipe_a_wa()
1597 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B && in gen11_dsi_sync_state()
1737 *pipe = PIPE_B; in gen11_dsi_get_hw_state()
Dintel_sprite.c457 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) in vlv_update_plane()
1772 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
1823 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
Dintel_dpll.c1537 intel_de_write(dev_priv, DPLL_MD(PIPE_B), in chv_enable_pll()
1547 (intel_de_read(dev_priv, DPLL(PIPE_B)) & in chv_enable_pll()
1585 if (pipe == PIPE_B) in vlv_prepare_pll()
Dvlv_dsi.c1059 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
1084 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1899 intel_encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
Dg4x_dp.c458 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { in intel_dp_link_down()
1395 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
/drivers/video/fbdev/intelfb/
Dintelfbhw.h183 #define PIPE_B 1 macro

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