Home
last modified time | relevance | path

Searched refs:PIPE_C (Results 1 – 23 of 23) sorted by relevance

/drivers/gpu/drm/i915/gvt/
Dhandlers.c890 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
893 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
896 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
1004 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
1027 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
2287 MMIO_D(PIPEDSL(PIPE_C), D_ALL); in init_generic_mmio_info()
2292 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2297 MMIO_D(PIPESTAT(PIPE_C), D_ALL); in init_generic_mmio_info()
2302 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); in init_generic_mmio_info()
2307 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); in init_generic_mmio_info()
[all …]
Dreg.h76 (((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \
84 (((reg) == 0x5008C || (reg) == 0x5009C) ? (PIPE_C) : \
Ddisplay.c52 pipe = PIPE_C; in get_edp_pipe()
625 [PIPE_C] = PIPE_C_VBLANK, in emulate_vblank_on_pipe()
629 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()
Dinterrupt.c455 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C));
Dcmd_parser.c1289 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE}, in gen8_decode_mi_display_flip()
1290 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE}, in gen8_decode_mi_display_flip()
1348 info->pipe = PIPE_C; in skl_decode_mi_display_flip()
1363 info->pipe = PIPE_C; in skl_decode_mi_display_flip()
/drivers/gpu/drm/i915/
Di915_pci.c110 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
117 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
124 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
448 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
609 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
685 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
847 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
883 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
903 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
915 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
[all …]
Dintel_pm.c522 case PIPE_C: in vlv_get_fifo_size()
1060 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) | in vlv_write_wm_values()
1061 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE)); in vlv_write_wm_values()
1063 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) | in vlv_write_wm_values()
1064 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC)); in vlv_write_wm_values()
1067 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) | in vlv_write_wm_values()
1068 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) | in vlv_write_wm_values()
1069 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) | in vlv_write_wm_values()
1972 wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1; in vlv_compute_pipe_wm()
2083 case PIPE_C: in vlv_atomic_update_fifo()
[all …]
Dintel_device_info.c274 runtime->num_scalers[PIPE_C] = 1; in intel_device_info_runtime_init()
300 runtime->num_sprites[PIPE_C] = 1; in intel_device_info_runtime_init()
333 info->pipe_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init()
348 info->pipe_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init()
Di915_trace.h47 __entry->frame[PIPE_C], __entry->scanline[PIPE_C])
74 __entry->frame[PIPE_C], __entry->scanline[PIPE_C])
171 __entry->frame[PIPE_C], __entry->scanline[PIPE_C])
Di915_irq.c1434 case PIPE_C: in i9xx_pipestat_irq_ack()
2403 pipe = PIPE_C; in gen11_dsi_te_interrupt_handler()
/drivers/gpu/drm/i915/display/
Dintel_pipe_crc.c186 case PIPE_C: in vlv_pipe_crc_ctl_reg()
250 case PIPE_C: in vlv_undo_pipe_scramble_reset()
Dintel_display_power.c1649 pipe = PIPE_C; in chv_dpio_cmn_power_well_enable()
1714 assert_pll_disabled(dev_priv, PIPE_C); in chv_dpio_cmn_power_well_disable()
1736 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; in assert_chv_phy_powergate()
3247 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3448 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3530 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3590 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3931 .hsw.irq_pipe_mask = BIT(PIPE_C),
4339 .hsw.irq_pipe_mask = BIT(PIPE_C),
4405 .hsw.irq_pipe_mask = BIT(PIPE_C),
[all …]
Dintel_display.h89 PIPE_C, enumerator
108 TRANSCODER_C = PIPE_C,
Dintel_fdi.c60 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); in ilk_check_fdi_lanes()
73 case PIPE_C: in ilk_check_fdi_lanes()
Dskl_universal_plane.c1774 if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C) in skl_plane_has_planar()
1835 return pipe != PIPE_C; in skl_plane_has_ccs()
1837 return pipe != PIPE_C && in skl_plane_has_ccs()
Dg4x_hdmi.c594 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_hdmi_init()
Dintel_cursor.c479 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && in i9xx_check_cursor()
Dicl_dsi.c877 case PIPE_C: in gen11_dsi_configure_transcoder()
1740 *pipe = PIPE_C; in gen11_dsi_get_hw_state()
Dintel_display_types.h1750 case PIPE_C: in vlv_pipe_to_channel()
Dg4x_dp.c1393 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_dp_init()
Dvlv_dsi.c1079 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) in intel_dsi_get_hw_state()
Dintel_ddi.c472 case PIPE_C: in intel_ddi_transcoder_func_reg_val_get()
736 *pipe_mask = BIT(PIPE_C); in intel_ddi_get_encoder_pipes()
Dintel_display.c2246 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) & in cpt_set_fdi_bc_bifurcation()
2274 case PIPE_C: in ivb_update_fdi_bc_bifurcation()
4618 (pipe == PIPE_B || pipe == PIPE_C)) in intel_set_transcoder_timings()
6056 trans_pipe = PIPE_C; in hsw_get_transcoder_state()