| /drivers/tty/serial/ |
| D | pmac_zilog.c | 169 write_zsreg(uap, R0, RES_EXT_INT); in pmz_load_zsregs()
170 write_zsreg(uap, R0, RES_EXT_INT); in pmz_load_zsregs()
237 write_zsreg(uap, R0, ERR_RES); in pmz_receive_chars()
310 ch = read_zsreg(uap, R0); in pmz_receive_chars()
326 status = read_zsreg(uap, R0); in pmz_status_handle()
327 write_zsreg(uap, R0, RES_EXT_INT); in pmz_status_handle()
360 unsigned char status = read_zsreg(uap, R0); in pmz_transmit_chars()
429 write_zsreg(uap, R0, RES_Tx_P); in pmz_transmit_chars()
459 write_zsreg(uap_a, R0, RES_H_IUS); in pmz_interrupt()
484 write_zsreg(uap_b, R0, RES_H_IUS); in pmz_interrupt()
[all …]
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| D | zs.c | 232 while ((read_zsreg(zport, R0) & Rx_CH_AV) && --loops) in zs_receive_drain()
242 while (!(read_zsreg(zport, R0) & Tx_BUF_EMP) && --loops) { in zs_transmit_drain()
324 status_a = read_zsreg(zport_a, R0); in zs_raw_get_ab_mctrl()
325 status_b = read_zsreg(zport_b, R0); in zs_raw_get_ab_mctrl()
421 write_zsreg(zport, R0, RES_Tx_P); in zs_raw_stop_tx()
498 write_zsreg(zport_a, R0, RES_EXT_INT); in zs_enable_ms()
547 avail = read_zsreg(zport, R0) & Rx_CH_AV; in zs_receive_chars()
572 write_zsreg(zport, R0, ERR_RES); in zs_receive_chars()
656 status = read_zsreg(zport, R0); in zs_status_handle()
693 write_zsreg(zport, R0, RES_EXT_INT); in zs_status_handle()
[all …]
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| D | zs.h | 60 #define R0 0 /* Register selects */ macro
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| D | ip22zilog.h | 39 #define R0 0 /* Register selects */ macro
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| D | sunzilog.h | 31 #define R0 0 /* Register selects */ macro
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| D | pmac_zilog.h | 127 #define R0 0 /* Register selects */ macro
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| D | ip22zilog.c | 216 write_zsreg(channel, R0, RES_EXT_INT); in __load_zsregs()
217 write_zsreg(channel, R0, RES_EXT_INT); in __load_zsregs()
705 (void) read_zsreg(channel, R0); in __ip22zilog_reset()
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| D | sunzilog.c | 249 write_zsreg(channel, R0, RES_EXT_INT); /* First Latch */ in __load_zsregs()
250 write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */ in __load_zsregs()
1342 (void) read_zsreg(channel, R0); in sunzilog_init_hw()
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| /drivers/net/hamradio/ |
| D | dmascc.c | 496 if (read_scc(priv, R0) & Tx_BUF_EMP) { in setup_adapter()
518 write_scc(priv, R0, RES_EXT_INT); in setup_adapter()
537 write_scc(priv, R0, RES_EXT_INT); in setup_adapter()
846 priv->rr0 = read_scc(priv, R0); in scc_open()
1006 write_scc(priv, R0, RES_EOM_L); in tx_on()
1015 while (read_scc(priv, R0) & Rx_CH_AV) in rx_on()
1043 write_scc(priv, R0, ERR_RES); in rx_on()
1104 write_scc(&info->priv[0], R0, RES_H_IUS); in z8530_isr()
1159 write_scc(priv, R0, ERR_RES); in rx_isr()
1164 while (read_scc(priv, R0) & Rx_CH_AV) { in rx_isr()
[all …]
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| D | scc.c | 401 OutReg(scc->ctrl, R0, RES_Tx_CRC); in scc_txint()
438 status = InReg(scc->ctrl,R0); in scc_exint()
654 OutReg(scc->ctrl,R0,RES_H_IUS); /* Reset Highest IUS */ in scc_isr()
703 OutReg(scc->ctrl,R0,RES_H_IUS); in scc_isr()
865 if(scc->kiss.softdcd || (InReg(scc->ctrl,R0) & DCD)) in init_channel()
880 scc->status = InReg(scc->ctrl,R0); /* read initial status */ in init_channel()
1254 OutReg(scc->ctrl, R0, RES_Tx_P); in t_maxkeyup()
2069 seq_printf(seq, "\tR %2.2x %2.2x XX ", InReg(scc->ctrl,R0), InReg(scc->ctrl,R1)); in scc_net_seq_show()
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| D | z8530.h | 7 #define R0 0 /* Register selects */ macro
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| /drivers/net/wan/ |
| D | z85230.c | 318 if (!(read_zsreg(c, R0) & 1)) in z8530_rx()
376 if (!(read_zsreg(c, R0) & 4)) in z8530_tx()
413 status = read_zsreg(chan, R0); in z8530_status()
514 status = read_zsreg(chan, R0); in z8530_dma_status()
615 u8 status = read_zsreg(chan, R0); in z8530_status_clear()
768 chk = read_zsreg(c, R0); in z8530_sync_close()
945 chk = read_zsreg(c, R0); in z8530_sync_dma_close()
1095 chk = read_zsreg(c, R0); in z8530_sync_txdma_close()
1173 if (read_zsreg(&dev->chanA, R0) & Tx_BUF_EMP) in do_z8530_init()
1290 c->status = read_zsreg(c, R0); in z8530_channel_load()
[all …]
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| D | z85230.h | 26 #define R0 0 /* Register selects */ macro
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| /drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_plane.c | 51 R0, enumerator
821 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; in dpu_plane_validate_multirect_v2()
830 if (dst[R1].y1 >= dst[R0].y2 + buffer_lines || in dpu_plane_validate_multirect_v2()
831 dst[R0].y1 >= dst[R1].y2 + buffer_lines) { in dpu_plane_validate_multirect_v2()
832 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; in dpu_plane_validate_multirect_v2()
837 drm_state[R0]->plane->base.id, in dpu_plane_validate_multirect_v2()
843 if (dpu_plane[R0]->is_virtual) { in dpu_plane_validate_multirect_v2()
844 pstate[R0]->multirect_index = DPU_SSPP_RECT_1; in dpu_plane_validate_multirect_v2()
847 pstate[R0]->multirect_index = DPU_SSPP_RECT_0; in dpu_plane_validate_multirect_v2()
851 DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n", in dpu_plane_validate_multirect_v2()
[all …]
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| /drivers/media/i2c/ |
| D | wm8739.c | 35 R0 = 0, R1, enumerator
114 wm8739_write(sd, R0, (vol_l & 0x1f) | mute); in wm8739_s_ctrl()
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| /drivers/regulator/ |
| D | slg51000-regulator.c | 350 enum { R0 = 0, R1, R2, REG_MAX }; in slg51000_irq_handler() enumerator
388 (evt[i][R0] & SLG51000_EVT_ILIM_FLAG_MASK)) { in slg51000_irq_handler()
400 (evt[SLG51000_SCTL_EVT][R0] & SLG51000_EVT_HIGH_TEMP_WARN_MASK)) { in slg51000_irq_handler()
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| /drivers/media/dvb-frontends/ |
| D | drxk_hard.c | 162 u32 R0 = 0; in Frac28a() local
164 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ in Frac28a()
172 Q1 = (Q1 << 4) | (R0 / c); in Frac28a()
173 R0 = (R0 % c) << 4; in Frac28a()
176 if ((R0 >> 3) >= c) in Frac28a()
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| /drivers/media/dvb-frontends/drx39xyj/ |
| D | drxj.c | 1071 u32 R0 = 0; in frac28() local
1073 R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */ in frac28()
1079 Q1 = (Q1 << 4) | R0 / D; in frac28()
1080 R0 = (R0 % D) << 4; in frac28()
1083 if ((R0 >> 3) >= D) in frac28()
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