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Searched refs:RADEON_CP_RB_CNTL (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/radeon/
Drs600.c478 tmp = RREG32(RADEON_CP_RB_CNTL); in rs600_asic_reset()
479 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); in rs600_asic_reset()
482 WREG32(RADEON_CP_RB_CNTL, tmp); in rs600_asic_reset()
Dr300.c429 tmp = RREG32(RADEON_CP_RB_CNTL); in r300_asic_reset()
430 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); in r300_asic_reset()
433 WREG32(RADEON_CP_RB_CNTL, tmp); in r300_asic_reset()
Dr100.c1182 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); in r100_cp_init()
1188 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); in r100_cp_init()
1205 WREG32(RADEON_CP_RB_CNTL, tmp); in r100_cp_init()
2578 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_asic_reset()
2579 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); in r100_asic_reset()
2582 WREG32(RADEON_CP_RB_CNTL, tmp); in r100_asic_reset()
4006 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_restore_sanity()
4008 WREG32(RADEON_CP_RB_CNTL, 0); in r100_restore_sanity()
Dradeon_reg.h3297 #define RADEON_CP_RB_CNTL 0x0704 macro