Searched refs:RCC_PLL1DIVR (Results 1 – 1 of 1) sorted by relevance
| /drivers/clk/ |
| D | clk-stm32h7.c | 28 #define RCC_PLL1DIVR 0x30 macro
638 .offset_divr = RCC_PLL1DIVR,
957 M_ODF_F("pll1_p", "vco1", RCC_PLLCFGR, 16, RCC_PLL1DIVR, 9, 7,
959 M_ODF_F("pll1_q", "vco1", RCC_PLLCFGR, 17, RCC_PLL1DIVR, 16, 7,
961 M_ODF_F("pll1_r", "vco1", RCC_PLLCFGR, 18, RCC_PLL1DIVR, 24, 7,
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