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Searched refs:REG_UPDATE (Results 1 – 25 of 78) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_mmhubbub.c83 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, params->swlock); in mmhubbub2_config_mcif_buf()
86 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); in mmhubbub2_config_mcif_buf()
87 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub2_config_mcif_buf()
89 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, 0); in mmhubbub2_config_mcif_buf()
92 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); in mmhubbub2_config_mcif_buf()
93 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub2_config_mcif_buf()
95 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, 0); in mmhubbub2_config_mcif_buf()
98 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); in mmhubbub2_config_mcif_buf()
99 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub2_config_mcif_buf()
101 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, 0); in mmhubbub2_config_mcif_buf()
[all …]
Ddcn20_dwb.c83 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 1); in dwb2_config_dwb_cnv()
84 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_X, params->cnv_params.crop_x); in dwb2_config_dwb_cnv()
85 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_Y, params->cnv_params.crop_y); in dwb2_config_dwb_cnv()
86 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, params->cnv_params.crop_width); in dwb2_config_dwb_cnv()
87 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, params->cnv_params.crop_height); in dwb2_config_dwb_cnv()
89 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 0); in dwb2_config_dwb_cnv()
93 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_RATE, params->capture_rate); in dwb2_config_dwb_cnv()
96 REG_UPDATE(CNV_MODE, CNV_OUT_BPC, params->cnv_params.cnv_out_bpc); in dwb2_config_dwb_cnv()
118 REG_UPDATE(WB_ENABLE, WB_ENABLE, 1); in dwb2_enable()
127 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE); in dwb2_enable()
[all …]
Ddcn20_dpp.c81 REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0); in dpp2_power_on_obuf()
83 REG_UPDATE(OBUF_MEM_PWR_CTRL, in dpp2_power_on_obuf()
86 REG_UPDATE(DSCL_MEM_PWR_CTRL, in dpp2_power_on_obuf()
122 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp2_cnv_setup()
123 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp2_cnv_setup()
124 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp2_cnv_setup()
125 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp2_cnv_setup()
216 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); in dpp2_cnv_setup()
217 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); in dpp2_cnv_setup()
218 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); in dpp2_cnv_setup()
[all …]
Ddcn20_stream_encoder.c83 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc2_update_hdmi_info_packet()
90 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc2_update_hdmi_info_packet()
97 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc2_update_hdmi_info_packet()
104 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc2_update_hdmi_info_packet()
111 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, in enc2_update_hdmi_info_packet()
118 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, in enc2_update_hdmi_info_packet()
125 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, in enc2_update_hdmi_info_packet()
132 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, in enc2_update_hdmi_info_packet()
151 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); in enc2_stream_encoder_update_hdmi_info_packets()
225 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 1); in enc2_update_gsp7_128_info_packet()
[all …]
Ddcn20_optc.c55 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, in optc2_enable_crtc()
59 REG_UPDATE(CONTROL, in optc2_enable_crtc()
86 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, in optc2_set_timing_db_mode()
119 REG_UPDATE(OTG_GSL_CONTROL, in optc2_use_gsl_as_master_update_lock()
146 REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal); in optc2_set_gsl_source_select()
149 REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal); in optc2_set_gsl_source_select()
152 REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal); in optc2_set_gsl_source_select()
183 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, in optc2_set_dsc_config()
189 REG_UPDATE(OPTC_WIDTH_CONTROL, in optc2_set_dsc_config()
212 REG_UPDATE(OTG_H_TIMING_CNTL, in optc2_set_odm_bypass()
[all …]
Ddcn20_dwb_scl.c751 REG_UPDATE(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, h_ratio_luma); in dwb_program_horz_scalar()
754 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, h_taps_luma - 1); in dwb_program_horz_scalar()
755 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, h_taps_chroma - 1); in dwb_program_horz_scalar()
777 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, h_init_phase_luma_int); in dwb_program_horz_scalar()
778 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, h_init_phase_luma_frac); in dwb_program_horz_scalar()
779 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, h_init_phase_chroma_int); in dwb_program_horz_scalar()
780 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, h_init_phase_chroma_frac); in dwb_program_horz_scalar()
829 REG_UPDATE(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, v_ratio_luma); in dwb_program_vert_scalar()
832 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, v_taps_luma - 1); in dwb_program_vert_scalar()
833 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, v_taps_chroma - 1); in dwb_program_vert_scalar()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_mmhubbub.c97 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, 1); in mmhubbub3_warmup_mcif()
100 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false); in mmhubbub3_warmup_mcif()
110 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); in mmhubbub3_config_mcif_buf()
111 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub3_config_mcif_buf()
114 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); in mmhubbub3_config_mcif_buf()
115 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub3_config_mcif_buf()
118 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); in mmhubbub3_config_mcif_buf()
119 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub3_config_mcif_buf()
122 REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1])); in mmhubbub3_config_mcif_buf()
123 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub3_config_mcif_buf()
[all …]
Ddcn30_vpg.c78 REG_UPDATE(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_CLR, 1); in vpg3_update_generic_info_packet()
81 REG_UPDATE(VPG_GENERIC_PACKET_ACCESS_CTRL, in vpg3_update_generic_info_packet()
111 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
115 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
119 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
123 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
127 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
131 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
135 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
139 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
[all …]
Ddcn30_dio_stream_encoder.c103 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc3_update_hdmi_info_packet()
110 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc3_update_hdmi_info_packet()
117 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc3_update_hdmi_info_packet()
124 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc3_update_hdmi_info_packet()
131 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, in enc3_update_hdmi_info_packet()
138 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, in enc3_update_hdmi_info_packet()
145 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, in enc3_update_hdmi_info_packet()
152 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, in enc3_update_hdmi_info_packet()
159 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7, in enc3_update_hdmi_info_packet()
166 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7, in enc3_update_hdmi_info_packet()
[all …]
Ddcn30_dwb.c76 REG_UPDATE(FC_MODE_CTRL, FC_WINDOW_CROP_EN, 1); in dwb3_config_fc()
77 REG_UPDATE(FC_WINDOW_START, FC_WINDOW_START_X, params->cnv_params.crop_x); in dwb3_config_fc()
78 REG_UPDATE(FC_WINDOW_START, FC_WINDOW_START_Y, params->cnv_params.crop_y); in dwb3_config_fc()
79 REG_UPDATE(FC_WINDOW_SIZE, FC_WINDOW_WIDTH, params->cnv_params.crop_width); in dwb3_config_fc()
80 REG_UPDATE(FC_WINDOW_SIZE, FC_WINDOW_HEIGHT, params->cnv_params.crop_height); in dwb3_config_fc()
82 REG_UPDATE(FC_MODE_CTRL, FC_WINDOW_CROP_EN, 0); in dwb3_config_fc()
86 REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_RATE, params->capture_rate); in dwb3_config_fc()
97 REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, 1); in dwb3_enable()
111 REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE); in dwb3_enable()
114 REG_UPDATE(FC_FLOW_CTRL, FC_FIRST_PIXEL_DELAY_COUNT, 96); in dwb3_enable()
[all …]
Ddcn30_afmt.c53 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); in afmt3_setup_hdmi_audio()
68 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); in afmt3_setup_hdmi_audio()
138 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); in afmt3_se_audio_setup()
141 REG_UPDATE(AFMT_MEM_PWR, AFMT_MEM_PWR_FORCE, 0); in afmt3_se_audio_setup()
151 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); in afmt3_audio_mute_control()
160 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); in afmt3_audio_info_immediate_update()
169 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); in afmt3_setup_dp_audio()
178 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); in afmt3_setup_dp_audio()
181 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); in afmt3_setup_dp_audio()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.c77 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); in dce110_update_generic_info_packet()
97 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); in dce110_update_generic_info_packet()
102 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, in dce110_update_generic_info_packet()
143 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
147 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
151 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
155 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
159 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
163 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
167 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
[all …]
Ddce_dmcu.c118 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); in dce_get_dmcu_psr_state()
131 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); in dce_get_dmcu_psr_state()
150 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
153 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
157 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_dmcu_set_psr_enable()
200 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
204 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
208 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
212 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
229 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
[all …]
Ddce_ipp.c51 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); in dce_ipp_cursor_set_position()
55 REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable); in dce_ipp_cursor_set_position()
66 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); in dce_ipp_cursor_set_position()
77 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); in dce_ipp_cursor_set_attributes()
136 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); in dce_ipp_cursor_set_attributes()
146 REG_UPDATE(PRESCALE_GRPH_CONTROL, in dce_ipp_program_prescale()
162 REG_UPDATE(PRESCALE_GRPH_CONTROL, in dce_ipp_program_prescale()
166 REG_UPDATE(INPUT_GAMMA_CONTROL, in dce_ipp_program_prescale()
186 REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0); in dce_ipp_program_input_lut()
215 REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); in dce_ipp_program_input_lut()
[all …]
Ddce_mem_input.c150 REG_UPDATE(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, in dce_mi_program_pte_vm()
169 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in program_urgency_watermark()
184 REG_UPDATE(DPG_PIPE_ARBITRATION_CONTROL3, in dce60_program_urgency_watermark()
199 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in dce120_program_urgency_watermark()
218 REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, in dce60_program_nbp_watermark()
226 REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, in dce60_program_nbp_watermark()
237 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in program_nbp_watermark()
245 REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, in program_nbp_watermark()
250 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in program_nbp_watermark()
258 REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL, in program_nbp_watermark()
[all …]
Ddce_hwseq.c43 REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst], in dce_enable_fe_clock()
126 REG_UPDATE(BLND_CONTROL[blnd_inst], in dce_set_blender_mode()
141 REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, in dce_disable_sram_shut_down()
149 REG_UPDATE(DCFEV_CLOCK_CONTROL, in dce_underlay_clock_enable()
180 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
190 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
201 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.c68 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); in enc1_update_generic_info_packet()
87 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); in enc1_update_generic_info_packet()
91 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, in enc1_update_generic_info_packet()
123 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
127 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
131 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
135 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
139 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
143 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
147 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
[all …]
Ddcn10_opp.c168 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0); in opp1_set_pixel_encoding()
177 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2); in opp1_set_pixel_encoding()
292 REG_UPDATE(FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, 0); in opp1_program_fmt()
326 REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0); in opp1_program_stereo()
328 REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, active_width); in opp1_program_stereo()
336 REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, space2_size); in opp1_program_stereo()
338 REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, space1_size); in opp1_program_stereo()
358 REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, oppbuf->active_width); in opp1_program_oppbuf()
366 REG_UPDATE(OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, oppbuf->mso_segmentation); in opp1_program_oppbuf()
369 REG_UPDATE(OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, oppbuf->mso_overlap_pixel_num); in opp1_program_oppbuf()
[all …]
Ddcn10_hubp.c74 REG_UPDATE(DCHUBP_CNTL, in hubp1_disconnect()
77 REG_UPDATE(CURSOR_CONTROL, in hubp1_disconnect()
86 REG_UPDATE(DCHUBP_CNTL, in hubp1_disable_control()
107 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); in hubp1_clear_underflow()
115 REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); in hubp1_set_hubp_blank_en()
262 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
266 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
271 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
277 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
282 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
[all …]
Ddcn10_dpp_cm.c356 REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK, in dpp1_cm_configure_regamma_lut()
358 REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK, in dpp1_cm_configure_regamma_lut()
589 REG_UPDATE(CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, 8); in dpp1_enable_cm_block()
590 REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0); in dpp1_enable_cm_block()
603 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0); in dpp1_set_degamma()
606 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1); in dpp1_set_degamma()
609 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2); in dpp1_set_degamma()
612 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3); in dpp1_set_degamma()
630 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3); in dpp1_degamma_ram_select()
632 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 4); in dpp1_degamma_ram_select()
[all …]
Ddcn10_dpp.c274 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3); in dpp1_set_degamma_format_float()
275 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1); in dpp1_set_degamma_format_float()
277 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2); in dpp1_set_degamma_format_float()
278 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0); in dpp1_set_degamma_format_float()
390 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp1_cnv_setup()
411 REG_UPDATE(CURSOR_CONTROL, in dpp1_cnv_setup()
413 REG_UPDATE(CURSOR0_CONTROL, in dpp1_cnv_setup()
431 REG_UPDATE(CURSOR0_COLOR0, in dpp1_set_cursor_attributes()
433 REG_UPDATE(CURSOR0_COLOR1, in dpp1_set_cursor_attributes()
476 REG_UPDATE(CURSOR0_CONTROL, in dpp1_set_cursor_position()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn302/
Ddcn302_hwseq.c57 REG_UPDATE(DOMAIN1_PG_CONFIG, in dcn302_dpp_pg_control()
65 REG_UPDATE(DOMAIN3_PG_CONFIG, in dcn302_dpp_pg_control()
73 REG_UPDATE(DOMAIN5_PG_CONFIG, in dcn302_dpp_pg_control()
81 REG_UPDATE(DOMAIN7_PG_CONFIG, in dcn302_dpp_pg_control()
89 REG_UPDATE(DOMAIN9_PG_CONFIG, in dcn302_dpp_pg_control()
114 REG_UPDATE(DOMAIN0_PG_CONFIG, in dcn302_hubp_pg_control()
122 REG_UPDATE(DOMAIN2_PG_CONFIG, in dcn302_hubp_pg_control()
130 REG_UPDATE(DOMAIN4_PG_CONFIG, in dcn302_hubp_pg_control()
138 REG_UPDATE(DOMAIN6_PG_CONFIG, in dcn302_hubp_pg_control()
146 REG_UPDATE(DOMAIN8_PG_CONFIG, in dcn302_hubp_pg_control()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/
Dhw_gpio.c54 REG_UPDATE(MASK_reg, MASK, gpio->store.mask); in restore_registers()
55 REG_UPDATE(A_reg, A, gpio->store.a); in restore_registers()
56 REG_UPDATE(EN_reg, EN, gpio->store.en); in restore_registers()
107 REG_UPDATE(A_reg, A, value); in dal_hw_gpio_set_value()
114 REG_UPDATE(EN_reg, EN, ~value); in dal_hw_gpio_set_value()
151 REG_UPDATE(EN_reg, EN, 0); in dal_hw_gpio_config_mode()
152 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
157 REG_UPDATE(A_reg, A, 0); in dal_hw_gpio_config_mode()
158 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
163 REG_UPDATE(A_reg, A, 0); in dal_hw_gpio_config_mode()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_dio_link_encoder.c80 REG_UPDATE(DIO_LINKA_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
83 REG_UPDATE(DIO_LINKA_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
85 REG_UPDATE(DIO_LINKA_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
90 REG_UPDATE(DIO_LINKB_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
93 REG_UPDATE(DIO_LINKB_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
95 REG_UPDATE(DIO_LINKB_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
100 REG_UPDATE(DIO_LINKC_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
103 REG_UPDATE(DIO_LINKC_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
105 REG_UPDATE(DIO_LINKC_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
110 REG_UPDATE(DIO_LINKD_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
[all …]
/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_hw_sequencer.c208 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
211 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
214 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()
219 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
222 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
225 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()
230 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
233 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
236 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()

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