| /drivers/reset/ |
| D | reset-rzg2l-usbphy-ctrl.c | 16 #define RESET 0x000 macro
51 val = readl(base + RESET); in rzg2l_usbphy_ctrl_assert()
55 writel(val, base + RESET); in rzg2l_usbphy_ctrl_assert()
70 val = readl(base + RESET); in rzg2l_usbphy_ctrl_deassert()
74 writel(val, base + RESET); in rzg2l_usbphy_ctrl_deassert()
88 return !!(readl(priv->base + RESET) & port_mask); in rzg2l_usbphy_ctrl_status()
151 val = readl(priv->base + RESET); in rzg2l_usbphy_ctrl_probe()
153 writel(val, priv->base + RESET); in rzg2l_usbphy_ctrl_probe()
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| /drivers/pcmcia/ |
| D | pxa2xx_colibri.c | 39 RESET = 5, enumerator
93 gpio_set_value(colibri_pcmcia_gpios[RESET].gpio, in colibri_pcmcia_configure_socket()
126 colibri_pcmcia_gpios[RESET].gpio = COLIBRI270_RESET_GPIO; in colibri_pcmcia_init()
134 colibri_pcmcia_gpios[RESET].gpio = COLIBRI320_RESET_GPIO; in colibri_pcmcia_init()
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| /drivers/misc/altera-stapl/ |
| D | altera-jtag.c | 35 /* RESET */ { RESET, IDLE },
44 /* IRSELECT */ { RESET, IRCAPTURE },
307 } else if (state == RESET) in altera_goto_jstate()
354 tms = (wait_state == RESET) ? TMS_HIGH : TMS_LOW; in altera_wait_cycles()
598 case RESET: in altera_irscan()
697 case RESET: in altera_swap_ir()
801 case RESET: in altera_drscan()
892 case RESET: in altera_swap_dr()
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| D | altera-jtag.h | 18 RESET = 0, enumerator
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| /drivers/media/i2c/ |
| D | ov2640.c | 128 #define RESET 0xE0 /* Reset */ macro
386 { RESET, RESET_JPEG | RESET_DVP },
504 { RESET, RESET_DVP },
529 { RESET, 0x00}
605 { RESET, 0x00 },
615 { RESET, 0x00 },
623 { RESET, 0x00 },
631 { RESET, 0x00 },
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| D | mt9m111.c | 433 return reg_write(RESET, MT9M111_RESET_CHIP_ENABLE); in mt9m111_enable()
441 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); in mt9m111_reset()
443 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC); in mt9m111_reset()
445 ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE in mt9m111_reset()
924 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); in mt9m111_suspend()
926 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC | in mt9m111_suspend()
930 ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE); in mt9m111_suspend()
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| /drivers/iio/chemical/ |
| D | sps30.c | 35 RESET, enumerator
72 if (state->state == RESET) { in sps30_do_meas()
98 state->state = RESET; in sps30_do_reset()
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| /drivers/input/keyboard/ |
| D | qt1070.c | 39 #define RESET 0x39 macro
186 qt1070_write(client, RESET, 1); in qt1070_probe()
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| /drivers/media/dvb-frontends/ |
| D | zl10353_priv.h | 45 RESET = 0x55, enumerator
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| D | mt352_priv.h | 66 RESET = 0x50, enumerator
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| D | bcm3510.c | 256 if (ap.APSTAT1_a2.RESET || ap.APSTAT1_a2.IDLE || ap.APSTAT1_a2.STOP || hab.HABSTAT_a8.HABR) {
686 bcm3510_readB(st,0xa0,&v); v.HCTL1_a0.RESET = 1; in bcm3510_reset()
696 if (v.APSTAT1_a2.RESET) in bcm3510_reset()
720 if (!v.APSTAT1_a2.RESET) in bcm3510_clear_reset()
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| D | mt312_priv.h | 35 RESET = 21, enumerator
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| D | bcm3510_priv.h | 40 u8 RESET :1; member
62 u8 RESET :1; member
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| /drivers/net/wireless/ath/ath9k/ |
| D | link.c | 49 ath_dbg(ath9k_hw_common(sc->sc_ah), RESET, in ath_tx_complete_check()
83 ath_dbg(common, RESET, in ath_hw_check()
105 ath_dbg(common, RESET, "PLL WAR, resetting the chip\n"); in ath_hw_pll_rx_hang_check()
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| D | ar9003_phy.c | 2066 ath_dbg(common, RESET, "Disabled BB Watchdog\n"); in ar9003_hw_bb_watchdog_config()
2102 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n", in ar9003_hw_bb_watchdog_config()
2131 ath_dbg(common, RESET, in ar9003_hw_bb_watchdog_dbg_info()
2133 ath_dbg(common, RESET, in ar9003_hw_bb_watchdog_dbg_info()
2145 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", in ar9003_hw_bb_watchdog_dbg_info()
2148 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n", in ar9003_hw_bb_watchdog_dbg_info()
2153 ath_dbg(common, RESET, in ar9003_hw_bb_watchdog_dbg_info()
2157 ath_dbg(common, RESET, "==== BB update: done ====\n\n"); in ar9003_hw_bb_watchdog_dbg_info()
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| D | hw.c | 445 ath_dbg(common, RESET, "serialize_regmode is %d\n", in ath9k_hw_init_config()
1057 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", in ath9k_hw_init_global_settings()
1333 ath_dbg(ath9k_hw_common(ah), RESET, in ath9k_hw_ar9330_reset_war()
1430 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); in ath9k_hw_set_reset()
1474 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); in ath9k_hw_set_reset_power_on()
1756 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", in ath9k_hw_init_desc()
1761 ath_dbg(common, RESET, "Setting CFG 0x%x\n", in ath9k_hw_init_desc()
1829 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", in ath9k_hw_do_fastcc()
2244 ath_dbg(common, RESET, "%s -> %s\n", in ath9k_hw_setpower()
3049 ath_dbg(ath9k_hw_common(ah), RESET, in ath9k_hw_reset_tsf()
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| /drivers/gpu/drm/hisilicon/kirin/ |
| D | dw_dsi_reg.h | 16 #define RESET 0 macro
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| /drivers/gpu/drm/radeon/ |
| D | rv740d.h | 56 #define RESET (1 << 30) macro
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| /drivers/firmware/arm_scmi/ |
| D | reset.c | 18 RESET = 0x4, enumerator
164 ret = ph->xops->xfer_get_init(ph, RESET, sizeof(*dom), 0, &t); in scmi_domain_reset()
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| /drivers/scsi/ |
| D | FlashPoint.c | 489 #define RESET BIT(7) macro
1739 if (hp_int & (FIFO | TIMEOUT | RESET | SCAM_SEL) || bm_status) { in FlashPoint_HandleInterrupt()
1744 (FIFO | TIMEOUT | RESET | SCAM_SEL)); in FlashPoint_HandleInterrupt()
2003 (BUS_FREE | RESET))) { in FPT_SccbMgr_bad_isr()
2009 else if (p_int & RESET) { in FPT_SccbMgr_bad_isr()
2723 (PHASE | RESET)) in FPT_sres()
2805 while (!(RDW_HARPOON((port + hp_intstat)) & (PHASE | RESET)) && in FPT_sres()
3721 while (!(RDW_HARPOON((p_port + hp_intstat)) & (BUS_FREE | RESET)) && in FPT_sxfrp()
3741 while (!(RDW_HARPOON((p_port + hp_intstat)) & (BUS_FREE | RESET))) { in FPT_sxfrp()
3752 if (!(RDW_HARPOON((p_port + hp_intstat)) & (BUS_FREE | RESET))) { in FPT_sxfrp()
[all …]
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| /drivers/staging/rts5208/ |
| D | xd.h | 33 #define RESET 0xff macro
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| /drivers/gpu/drm/bridge/synopsys/ |
| D | dw-mipi-dsi.c | 37 #define RESET 0 macro
600 dsi_write(dsi, DSI_PWR_UP, RESET); in dw_mipi_dsi_set_mode()
619 dsi_write(dsi, DSI_PWR_UP, RESET); in dw_mipi_dsi_disable()
650 dsi_write(dsi, DSI_PWR_UP, RESET); in dw_mipi_dsi_init()
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| /drivers/net/ethernet/sis/ |
| D | sis900.h | 46 RESET = 0x00000100, SWI = 0x00000080, RxRESET = 0x00000020, enumerator
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| /drivers/ufs/host/ |
| D | ufshcd-pci.c | 312 if (INTEL_DSM_SUPPORTED(host, RESET)) { in ufs_intel_device_reset()
354 if (INTEL_DSM_SUPPORTED(host, RESET)) { in ufs_intel_common_init()
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| /drivers/media/radio/wl128x/ |
| D | fmdrv_common.h | 70 #define RESET 102 macro
|