Searched refs:RVU_PF_VFME_INT_ENA_W1SX (Results 1 – 5 of 5) sorted by relevance
/drivers/net/ethernet/marvell/octeontx2/nic/ |
D | otx2_reg.h | 32 #define RVU_PF_VFME_INT_ENA_W1SX(a) (0x9C0 | (a) << 3) macro
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D | otx2_pf.c | 242 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); in otx2_register_flr_me_intr() 252 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), in otx2_register_flr_me_intr()
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/drivers/crypto/marvell/octeontx2/ |
D | otx2_cptpf_main.c | 81 RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(num_vfs)); in cptpf_enable_vf_flr_me_intrs() 94 RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(num_vfs - 64)); in cptpf_enable_vf_flr_me_intrs()
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/drivers/net/ethernet/marvell/octeontx2/af/ |
D | rvu_reg.h | 98 #define RVU_PF_VFME_INT_ENA_W1SX(a) (0x9C0 | (a) << 3) macro
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D | rvu.c | 3006 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs)); in rvu_enable_afvf_intr() 3018 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); in rvu_enable_afvf_intr()
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