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Searched refs:RVU_PF_VFPF_MBOX_INTX (Results 1 – 6 of 6) sorted by relevance

/drivers/crypto/marvell/octeontx2/
Dotx2_cptpf_main.c22 RVU_PF_VFPF_MBOX_INTX(0), ~0x0ULL); in cptpf_enable_vfpf_mbox_intr()
24 RVU_PF_VFPF_MBOX_INTX(1), ~0x0ULL); in cptpf_enable_vfpf_mbox_intr()
53 RVU_PF_VFPF_MBOX_INTX(0), ~0ULL); in cptpf_disable_vfpf_mbox_intr()
60 RVU_PF_VFPF_MBOX_INTX(1), ~0ULL); in cptpf_disable_vfpf_mbox_intr()
Dotx2_cptpf_mbox.c154 RVU_PF_VFPF_MBOX_INTX(i)); in otx2_cptpf_vfpf_mbox_intr()
163 0, RVU_PF_VFPF_MBOX_INTX(i), in otx2_cptpf_vfpf_mbox_intr()
/drivers/net/ethernet/marvell/octeontx2/nic/
Dotx2_pf.c556 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); in otx2_pfvf_mbox_intr_handler()
557 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); in otx2_pfvf_mbox_intr_handler()
565 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); in otx2_pfvf_mbox_intr_handler()
566 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); in otx2_pfvf_mbox_intr_handler()
662 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); in otx2_enable_pfvf_mbox_intr()
663 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); in otx2_enable_pfvf_mbox_intr()
682 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); in otx2_disable_pfvf_mbox_intr()
687 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); in otx2_disable_pfvf_mbox_intr()
Dotx2_reg.h22 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3) macro
/drivers/net/ethernet/marvell/octeontx2/af/
Drvu.c2457 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1)); in rvu_mbox_intr_handler()
2458 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr); in rvu_mbox_intr_handler()
2464 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0)); in rvu_mbox_intr_handler()
2465 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr); in rvu_mbox_intr_handler()
3000 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs)); in rvu_enable_afvf_intr()
3012 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64)); in rvu_enable_afvf_intr()
Drvu_reg.h88 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3) macro