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Searched refs:SCL (Results 1 – 10 of 10) sorted by relevance

/drivers/i2c/busses/
Di2c-acorn.c19 #define SCL 0x02 macro
32 u_int ioc_control = ioc_readb(IOC_CONTROL) & ~(SCL | SDA); in ioc_setscl()
36 ones |= SCL; in ioc_setscl()
38 ones &= ~SCL; in ioc_setscl()
47 u_int ioc_control = ioc_readb(IOC_CONTROL) & ~(SCL | SDA); in ioc_setsda()
62 return (ioc_readb(IOC_CONTROL) & SCL) != 0; in ioc_getscl()
87 force_ones = FORCE_ONES | SCL | SDA; in i2c_ioc_init()
Di2c-versatile.c20 #define SCL (1 << 0) macro
40 writel(SCL, i2c->base + (state ? I2C_CONTROLS : I2C_CONTROLC)); in i2c_versatile_setscl()
52 return !!(readl(i2c->base + I2C_CONTROL) & SCL); in i2c_versatile_getscl()
79 writel(SCL | SDA, i2c->base + I2C_CONTROLS); in i2c_versatile_probe()
DKconfig626 arch-neutral GPIO API to control the SCL and SDA lines.
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_i2c_sw.c31 #define SCL false macro
87 if (read_bit_from_ddc(ddc, SCL)) in wait_for_scl_high_sw()
115 write_bit_to_ddc(ddc_handle, SCL, true); in write_byte_sw()
120 write_bit_to_ddc(ddc_handle, SCL, false); in write_byte_sw()
136 write_bit_to_ddc(ddc_handle, SCL, true); in write_byte_sw()
147 write_bit_to_ddc(ddc_handle, SCL, false); in write_byte_sw()
170 write_bit_to_ddc(ddc_handle, SCL, true); in read_byte_sw()
178 write_bit_to_ddc(ddc_handle, SCL, false); in read_byte_sw()
199 write_bit_to_ddc(ddc_handle, SCL, true); in read_byte_sw()
204 write_bit_to_ddc(ddc_handle, SCL, false); in read_byte_sw()
[all …]
Ddce_transform.h76 SRI(SCL_MODE, SCL, id), \
77 SRI(SCL_TAP_CONTROL, SCL, id), \
78 SRI(SCL_CONTROL, SCL, id), \
79 SRI(SCL_BYPASS_CONTROL, SCL, id), \
80 SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
81 SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
82 SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
83 SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
84 SRI(SCL_COEF_RAM_SELECT, SCL, id), \
85 SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
[all …]
/drivers/rtc/
Drtc-rs5c313.c73 #define SCL SCSPTR1_SPB0DT macro
95 scsptr1_data = __raw_readb(SCSPTR1) | SCL; /* SCL:H */ in rs5c313_init_port()
116 scsptr1_data &= ~SCL; /* SCL:L */ in rs5c313_write_data()
119 scsptr1_data |= SCL; /* SCL:H */ in rs5c313_write_data()
136 scsptr1_data &= ~SCL; /* SCL:L */ in rs5c313_read_data()
139 scsptr1_data |= SCL; /* SCL:H */ in rs5c313_read_data()
/drivers/gpu/drm/amd/display/dc/gpio/
Dddc_regs.h171 DDC_I2C_REG_LIST(SCL)\
190 DDC_REG_LIST_DCN2(SCL)\
/drivers/scsi/
Dnsp32.c3236 nsp32_prom_set(data, SCL, 1); in nsp32_prom_start()
3241 nsp32_prom_set(data, SCL, 0); in nsp32_prom_start()
3247 nsp32_prom_set(data, SCL, 1); in nsp32_prom_stop()
3251 nsp32_prom_set(data, SCL, 0); in nsp32_prom_stop()
3258 nsp32_prom_set(data, SCL, 1 ); in nsp32_prom_write_bit()
3259 nsp32_prom_set(data, SCL, 0 ); in nsp32_prom_write_bit()
3268 nsp32_prom_set(data, SCL, 1); in nsp32_prom_read_bit()
3272 nsp32_prom_set(data, SCL, 0); in nsp32_prom_read_bit()
Dnsp32.h392 # define SCL BIT(0) macro
/drivers/auxdisplay/
DKconfig355 (SDA/SCL), while parallel ones use 2 or 3 wires for the control signals
406 int "Parallel port pin number & polarity connected to the LCD SCL signal (-17...17) "
411 LCD 'SCL' signal has been connected. It can be :
417 Default for the 'SCL' pin in custom profile is '1' (STROBE).